Fab desk

What a semiconductor fab actually is

Published 3 August 2026. Facts verified to 27 July 2026 unless dated otherwise.

Most coverage of India's first fab describes the money and skips the machine. The machine is the interesting part, and understanding it makes every schedule claim easier to judge.

The building is mostly not the cleanroom

Visitors expect a fab to be a big clean hall. In practice the cleanroom floor sits in the middle of a sandwich. Above it, a plenum pushes filtered air downward in a constant laminar flow. Below it, a sub-fab level roughly as large as the cleanroom itself holds pumps, abatement systems, chemical distribution and the unglamorous machinery that keeps the tools alive. Around all of it sits the central utility building: chillers, boilers, gas yards, water treatment and electrical distribution.

The practical consequence for anyone judging construction progress is that a fab looks finished long before it is. The shell and the cleanroom go up relatively fast; the fit-out, the hook-up of thousands of process connections, and the qualification of every utility take far longer and are almost invisible from outside the fence. This is the single most common reason observers misjudge fab timelines.

What a wafer actually does inside

A blank silicon wafer does not travel in a straight line. It loops. A single chip design requires hundreds of process steps, and the wafer passes through the same categories of tool many times over, building the device layer by layer:

• Deposition: add a thin film of material, sometimes only a few atoms thick.
• Lithography: project the circuit pattern onto light-sensitive resist coating that film.
• Etch: remove the material the pattern exposed, cutting the design into the layer.
• Doping: implant impurities that give silicon its electrical behaviour.
• Planarisation: polish the surface flat again so the next layer can be printed accurately.
• Cleaning and metrology: between almost every step, wash the wafer and measure whether the step worked.

Repeat that loop enough times and a pattern of transistors and wiring emerges. Each of the categories above has a dedicated page on this desk, because each is its own industry with its own suppliers, and those suppliers are what a fab region actually attracts.

Why cycle time and yield dominate the economics

Two numbers determine whether a fab makes money: how long a wafer takes to get through the loop, and what fraction of the chips on it work. Cycle time in a mature-node fab is typically measured in weeks, not days, because of the sheer number of steps and the queueing at bottleneck tools. Yield starts low on a new line and climbs as engineers eliminate defect sources, which is why every new fab has a learning period between its first wafers and its profitable ones.

This is the honest engineering reason a first-silicon date and a commercial-production date are different events separated by a long interval. At Dholera those two targets are guided to mid-2028 TARGET, and the gap between them is not bureaucratic padding, it is the yield ramp doing its work.

Why the surroundings matter as much as the building

A fab cannot run on a good building alone. It needs uninterrupted power of extreme quality, very large volumes of ultrapure water, a continuous supply of bulk and specialty gases, chemical logistics, and a workforce that can maintain vacuum systems at three in the morning. That dependency is why fabs anchor industrial regions rather than sit in them, and why our company register tracks the suppliers arriving around Dholera as closely as the anchor itself.