Guide

SCL Mohali: what India's one operating wafer fab actually does, and what the Rs 4,500 crore upgrade would change

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

India has been fabricating integrated circuits without interruption for most of thirty years, which is why the claim that the country has never made a chip is false as stated.

What SCL is, and the two errors this page exists to correct

The Semi-Conductor Laboratory at Mohali, in Punjab, is a government-owned wafer fabrication facility that has been producing integrated circuits for India's strategic and academic users for decades. Two opposite errors circulate about it, and both distort the current build-out debate.

The first error is that India has never fabricated a chip. It is false, and SCL is the reason. Wafers go in, patterned silicon comes out, and the parts land in real systems including spacecraft. The second error runs the other way: that because SCL exists, the fab now rising at Dholera is redundant or duplicative. That is equally wrong, and for reasons that are arithmetic rather than rhetorical. SCL and a commercial foundry differ by orders of magnitude in output, by a generation and a half in geometry, by wafer diameter, and most of all by customer base.

This page sets out what the public record actually supports about the facility: its institutional history with the dates that disagree, the 1989 fire and what the investigations found, what the line does today, why its node is a correct engineering choice rather than a legacy embarrassment, and what the Rs 4,500 crore modernisation announced by the Union government would and would not change.

The institutional record, with the dates that disagree

The enterprise was originally incorporated as Semiconductor Complex Limited. Accounts of its founding differ, and this record prints the difference rather than choosing. The Wikipedia entry on the laboratory, and the secondary Indian coverage that follows it, place a Union Cabinet decision to create the company in 1976, with production beginning in 1984 on technology from American Microsystems Inc, starting at five-micron CMOS. Those are secondary sources and are labelled as such here. The Observer Research Foundation's analysis of 22 June 2023 instead describes the government establishing the company in 1984 through licensing agreements with Hitachi, AMI and Rockwell. The Tribune's retrospective of 8 October 2022 gives 1984 as the establishment year.

Those readings are compatible if the sanction and the commissioning are treated as separate events, which is the normal shape of a public-sector industrial project in India. The licensing roster is a genuine open question, since the accounts differ over whether one foreign partner or three supplied the technology, and none of the sources examined here settles it.

The second institutional fact is the change of ownership and name. The Tribune's account records that in 2006 the organisation was restructured and renamed as a semiconductor laboratory within the Department of Space REPORTED. That move explains almost everything about what the facility is now used for. A fab inside the space department is not managed for wafer-start growth or commercial margin. It is managed to guarantee supply of parts that a national programme cannot buy freely on the open market, which is a different objective function entirely.

The fire of 7 February 1989, and the accounts that disagree

The plant's trajectory turns on one night. On 7 February 1989 a fire destroyed a large part of the facility's imported equipment, with the reported loss put at about Rs 60 crore. The Tribune's account of 8 October 2022 records that the plant restarted in 1997, eight years later.

Two versions of the cause circulate. The dramatic version, which survives in headlines describing the fire as mysterious, keeps sabotage in play and notes that Intelligence Bureau officials visited the plant without any conclusive public finding. The documented version, in The Tribune's reporting, is that the probe ruled out external sabotage and pointed to an accident or a short circuit, and that it found serious lapses in the facility's firefighting arrangements. This record prints no cause of its own, because the public record supports none.

What matters more than the cause is the consequence, and here the record is unambiguous. The Observer Research Foundation's assessment is that at the end of the 1980s India was roughly two years behind the leading semiconductor manufacturing technologies. Eight years without a line, in an industry then shrinking feature sizes on a two-year cadence and in an economy short of foreign exchange and constrained by export controls on tools, converted a recoverable gap into a permanent one. The same account records that the revival which followed produced only a limited number of chips for the space programme.

The lesson generalises, and it is the reason this desk pays close attention to the physical plant at Dholera rather than only to its financing. A fab is a tool set inside a building. The tools are irreplaceable on any short timescale, they are import-dependent, and their loss is not insurable in schedule terms. The wider history is set out at India's semiconductor history.

What the line actually does today

SCL's current capability is public in outline and unpublished in detail, and the outline is enough to place it correctly.

• Node. The fabrication line runs at 180nm CMOS DURABLE.
• Wafer size. Eight-inch, that is 200mm, per press reporting rather than a published company specification.
• Output. Press reporting puts wafer starts at roughly 600 per month REPORTED. No official capacity figure has been published that this desk has examined.
• Academic use. A Lok Sabha reply of 1 April 2026 records that of 211 chips taped out by 75 Indian academic institutions using government-provided design tools, 149 were fabricated at 180nm at SCL and 62 at overseas foundries DURABLE.
• Space work. The Vikram 3201 space-grade processor was fabricated at SCL on a 180nm process and presented at Semicon India in September 2025 DURABLE.

That last item is the most legible demonstration of what the facility is for. A domestically fabricated processor for launch vehicle avionics is not a technology-demonstration curiosity. It is import substitution in the one category where import substitution is strategically load-bearing, because export-controlled radiation-hardened parts are exactly the components a space programme cannot rely on buying. The space side of this is developed at ISRO and space chips.

Why 180nm is the correct node for this work

Readers who follow consumer chip coverage see 180nm and read obsolescence. In the application SCL serves, the larger geometry is the specification rather than the compromise, and the physics is straightforward.

A transistor's vulnerability to a single high-energy particle depends on how much charge is stored in the node that a strike can disturb. Larger devices hold more charge, so the charge deposited by an incident particle is a smaller fraction of the stored value and is less likely to flip a stored bit or corrupt a logic state. Larger geometries also tolerate the cumulative dose that degrades transistor thresholds over years in orbit. Radiation-hardened parts for space and defence are routinely built on nodes that commercial products abandoned two decades ago, and they are built that way deliberately.

The commercial logic points the same direction for a different reason. Qualification cycles for strategic parts run for years, design libraries are long-lived, and volumes are small. A line whose customers need supply assurance across a fifteen-year programme has no incentive to chase a node transition that would obsolete its qualified library. Why mature geometries persist across the whole industry, not only in strategic work, is examined at why mature nodes matter.

The Rs 4,500 crore modernisation: announced, budgeted, tendered

SCL is now the subject of the largest upgrade programme in its history, and the components sit at different levels of certainty.

The Union government has announced an investment of Rs 4,500 crore for the modernisation of SCL Mohali, carried on the Press Information Bureau wire under release 2196011 with an accompanying assurance that the facility will not be privatised, and mirrored on the Ministry of Electronics and Information Technology's Digital India newsroom. The Tribune reports the programme as about Rs 4,500 crore over three years REPORTED. Reporting places the announcement in late 2025, with the electronics and information technology minister and the minister of state associated with the review.

Three further elements are reported rather than confirmed by an instrument this desk has examined, and are tiered accordingly. Coverage of the Union Budget for 2026-27 records Rs 900 crore earmarked for SCL in that financial year as part of the wider programme REPORTED. The stated ambition includes a very large increase in wafer output, described in reporting as a target of about one hundred times current levels, alongside a training centre, a commercial production unit and a research and development facility under the India Semiconductor Mission TARGET. And the centre has reportedly sought a further land parcel of about 25 acres from the Punjab government to accommodate expansion.

On the procurement itself, coverage verified by this desk on 25 August 2026 records that Outlook Business reported Tata Semiconductor and Israel's Tower Semiconductor shortlisted for the first part of a revamp tender put at about Rs 4,000 crore REPORTED. A shortlist is not an award. The signal to watch is a signed contract with a scope, because that is the document that would convert a budget line into a dated engineering programme.

What modernising a legacy line physically involves is worth stating, because it explains why the sum is large for a plant of this size. A line built around a 1980s toolset carries equipment whose vendors no longer support it, spare parts sourced from a resale market, and control software that cannot talk to modern factory systems. Modernisation therefore means replacing tools rather than refurbishing them, rebuilding the facility systems that feed them, which is ultrapure water, bulk and specialty gases, chemical distribution and abatement, and requalifying every process step afterwards, because a replaced tool does not reproduce its predecessor's results without a new recipe. That last step is the slow one. A fab that has been running qualified processes for strategic customers cannot simply swap a tool and resume, since every part built on the new tool has to be re-proven against the qualification its customers rely on.

The reported direction of the money is more informative than its size. The programme as described expands capacity and capability around the existing line for strategic and domestic users rather than pursuing an advanced node. That is a sober choice and it is consistent with what the facility is for. A hundredfold increase from roughly 600 wafer starts per month would still leave the line far below the scale of a commercial foundry, which is the arithmetic the next section sets out.

SCL against the commercial wave, in numbers

Placing the two side by side is the fastest way to end the redundancy argument.

The output ratio is roughly eighty to one before wafer area is accounted for, and a 300mm wafer carries about 2.25 times the area of a 200mm wafer, since area scales with the square of the diameter, which widens the gap further when counted in dies. The customer relationship differs just as sharply: SCL supplies a national programme and university users, while a commercial foundry must win, qualify and retain external buyers who can take their volume elsewhere. On the Dholera node question there is an unresolved contradiction in the public record, with Bloomberg reporting on 17 July 2026 that the fab opens mostly at 90nm against Tata's official range of 28 to 110nm and the chairman's annual report reference to starting at 28nm. This record presents that contradiction rather than resolving it.

Where the two genuinely touch is talent and design enablement. A domestic 180nm line that fabricates academic tape-outs produces engineers who have taped out a real design and seen silicon come back, which is the single most useful preparation for a commercial fab's process and product teams. The 149 academic chips in the 1 April 2026 reply are a workforce statistic as much as a manufacturing one.

What is not public

Several things a reader might reasonably want are simply not disclosed, and the honest course is to name them. SCL publishes no audited wafer-start capacity that this desk has examined, so the roughly 600 per month figure rests on press reporting. No official confirmation of wafer diameter was located in the sources checked, which is why eight inches is carried as reported. The modernisation programme's technical scope, meaning which tools, which added capability and which target node, has not been published. No contract award under the revamp tender has been announced. And the plant's yield, defect density and customer list are not public, as they are not for most strategic facilities anywhere.

What this desk will watch

Four events would change the entries above. A signed modernisation contract with a named scope, which would convert a budget announcement into an engineering programme. Any published statement of a target node or wafer size after the upgrade, which would tell you whether the programme is capacity expansion or capability change. Confirmation of the Punjab land transfer, which is the physical precondition for expansion. And any statement placing SCL output inside a commercial supply chain rather than a strategic one, which would be the genuine change of category. Until those arrive, the correct summary is the one at the top of this page: India has an operating fab, it is small, it is strategic, and its existence answers a different question from the one the Dholera project is being built to answer, as set out at when will India make its first chip.