Company file
Vedanta and Dholera
Published 3 August 2026. Facts verified to 27 July 2026 unless dated otherwise.
Vedanta semiconductor status, told straight: the Vedanta-Foxconn JV collapsed in 2023, a solo Vedanta Dholera fab claim of about Rs 1.
The Vedanta-Foxconn semiconductor joint venture collapsed in 2023 when Foxconn exited. A solo Vedanta fab at Dholera, reported at about Rs 1.54 lakh crore on 40 nm with a first chip around 2027, remains an announced claim, not a confirmed build.
Status tier: REPORTED
The question people actually search
"Vedanta semiconductor" draws thousands of searches a month, and much of what ranks for it is either outdated or promotional. The clean version: the JV that made 2022's headlines no longer exists in that form. Foxconn walked in 2023. What survives is a restructured solo Vedanta ambition that has been reported but not confirmed as a build, and it should never be presented alongside the Tata fab as an equal.
The confirmed Dholera fab is Tata + PSMC
One project at Dholera has Cabinet approval, a signed Fiscal Support Agreement, a notified SEZ and construction underway: Tata Electronics with PSMC, Rs 91,000 crore, DURABLE. If the Vedanta claim ever hardens into approvals and ground activity, this page will upgrade it the same day the sourcing does.
Common confusion worth killing: Micron's plant is at Sanand, near Ahmedabad, not at Dholera. Full answer here.
What this record actually holds on the Vedanta-Foxconn venture
The verified core is short and worth stating plainly before anything is built on top of it. A semiconductor joint venture between Vedanta and Foxconn existed, it collapsed in 2023, and the collapse took the form of Foxconn exiting the structure REPORTED. Everything a reader normally wants beyond that, the signature dates, the exact shareholding, the incentive application numbers, the internal reasons each side gave, sits outside what this publication has verified to primary sources, and we will not manufacture a timeline to fill the gap. A chronology assembled from secondary retellings of secondary retellings is how the Dholera information environment became unreliable in the first place.
What can be said with confidence is structural. A fab venture of that kind moves through a recognisable sequence: a memorandum with a state government that secures land and state-level incentives, an application into the central incentive scheme, a technology licensing arrangement with an established process owner, a final investment decision by each shareholder, then ground-breaking and tool ordering. Each of those is a separate gate, and a venture can pass the early ones loudly while failing a later one quietly. What the 2023 exit establishes is only that the venture did not complete the sequence. It does not establish which gate stopped it, and that distinction matters for anyone reading the current crop of solo Vedanta claims.
Why fab joint ventures fail, first on the technology partner
The most common failure mode in a first-time fab venture is the absence of a real process owner. A wafer fab does not run on capital and buildings. It runs on a process flow, a process design kit that customers can design against, a device library, and several thousand recipe-level parameters that only exist inside a company that has already yielded that process at volume. Buying tools does not buy any of that. Neither does hiring individually excellent engineers, because the asset is institutional rather than personal.
This is where contract manufacturing credentials mislead. Excellence at electronics assembly, at back-end packaging, or at systems integration is genuine engineering competence, but it is competence in a different discipline from front-end wafer processing. An assembly partner brings scale, discipline and customer relationships. It does not bring a qualified 28 nanometre or 40 nanometre process, because it does not own one. When a venture is structured with a capital partner and an assembly partner but no licensor with a proven node, the technology has to come from somewhere later, and "later" is exactly where such ventures tend to break.
The contrast with the confirmed Dholera project is instructive rather than rhetorical. Tata Electronics contracted a technology transfer with Powerchip Semiconductor Manufacturing Corporation of Taiwan and completed that transfer agreement on 26 September 2024 DURABLE. DigiTimes reported in January 2025 that PSMC expects more than NT twenty billion, roughly six hundred and twenty million US dollars, from consulting, technology transfer and training across the lifecycle REPORTED. That figure is useful precisely because it is large. It is one public indication of what a real process transfer is worth, and it is the line item that ventures without a licensor never carry at all.
Capital, and why fab money behaves unlike any other industrial money
A fab consumes capital in a shape that most industrial balance sheets are not built for. Civil works and cleanroom shell come first, then process tools arrive in a compressed window, then there is a long unproductive stretch of installation, hook-up, process qualification and yield learning before a single wafer can be invoiced. Depreciation begins when tools are commissioned, not when revenue starts, so the profit and loss statement takes the full weight of the asset base during the period when output is worthless. Early wafers are scrapped by design, because yield learning is what they are for.
This is why a fab's financing structure is scrutinised harder than its headline number. A promoter carrying leverage elsewhere, or dependent on cyclical commodity cash flows, is structurally poorly matched to an asset that will absorb money for four to five years before it returns any. The relevant question is never whether an announced figure is impressive. It is whether the equity is committed, whether the debt is tied to milestones the project can actually hit, and whether the subsidy is contractual rather than aspirational.
On the confirmed project, that last point has a documented answer. The Union Cabinet approved the Rs 91,000 crore Tata Electronics and PSMC fab on 29 February 2024 DURABLE, and a Fiscal Support Agreement committing fifty per cent central fiscal support was signed on 5 March 2025 DURABLE. The Gujarat Semiconductor Policy 2022-27 then adds forty per cent of the capital assistance approved by the centre, stacking on top rather than replacing it DURABLE. Announced capital and contracted capital are different species, and only the second survives a downturn.
Node choice is a commercial decision, not a claim to status
Node numbers are the most misread figures in this sector. A smaller number is not automatically a better business. Leading-edge nodes carry brutal tool costs, thinner customer lists and shorter windows before the next node erodes pricing. Mature nodes run on largely depreciated equipment elsewhere in the world, which sets a hard price ceiling a new entrant must live under, but they also carry stable, long-lived demand in power management, automotive, industrial control and microcontrollers, where qualification cycles are slow and customers do not migrate casually.
For a first fab, the sequencing question is more important than the destination. Yield learning, contamination control, metrology discipline and equipment uptime all have to be built as organisational habits, and they are cheaper to build at a relaxed geometry. This is the substance behind the disagreement now visible in the public record on the Tata project. Bloomberg reported on 17 July 2026, carried by Outlook Business, that the fab will open mostly at 90 nanometres rather than 28 REPORTED, and TrendForce confirmed the account on 20 July 2026 REPORTED. A Tata spokesperson said the plan "has always been to start with 55nm and 90nm before introducing 28nm" REPORTED, and PSMC's Eric Tang noted that transfers are "typically introduced gradually, starting with more mature nodes" REPORTED. Against that, Tata Sons chairman N Chandrasekaran wrote in the annual report for the year ended March 2025 that "We have chosen to start our chip journey at the 28nm node" DURABLE. Both statements are on the record. The honest reading is that the ramp plan and the investor-facing narrative are not perfectly aligned, which is common and worth watching rather than scandalous.
The relevance to any solo Vedanta claim is direct. A stated node with no named licensor, no process design kit and no qualification schedule is a marketing number. A stated node accompanied by a signed transfer, a training pipeline and a tool vendor relationship is a plan.
Customer commitments, the thing press releases never contain
A merchant foundry is a service business. It sells capacity, and capacity has to be pre-sold, because the alternative is an idle cleanroom burning fixed cost. Customers do not commit casually. A fabless designer must port its design to the new fab's process design kit, run test silicon, wait for parametric data, and then requalify at the system level. Automotive parts add a further stress and reliability qualification layer that runs for many months and is not compressible by enthusiasm. That is why anchor customers are usually locked in long before first silicon, and why their absence is the most reliable early warning that a fab project is announcement rather than build.
On the Dholera project the partner list is real but should be read for what each item legally is:
- ASML, a memorandum of understanding announced on 16 May 2026 by both the ASML press release and the Tata Electronics newsroom, naming 28, 40, 55, 90 and 110 nanometre nodes REPORTED. See the ASML file.
- Intel, an explicitly non-binding exploratory memorandum dated 8 December 2025, to explore manufacturing and packaging of Intel products REPORTED.
- Qualcomm, a partnership announced on 20 February 2026 for automotive modules in India, with scope and Dholera linkage unverified REPORTED.
- ROHM, a strategic partnership announced on 22 December 2025, scope unverified REPORTED.
None of those is a published volume commitment with pricing, and no valued equipment purchase order for the fab has been made public either DURABLE. That is a gap in the public record rather than proof of a problem, but it is the gap a serious reader should keep open.
What the ISM approval process actually requires
The India Semiconductor Mission route has three stages that are routinely collapsed into one in coverage. Approval is the first: a proposal is assessed and then cleared by the Union Cabinet, which is the visible, quotable event. Contracting is the second: a fiscal support agreement converts the approval into an enforceable commitment with defined obligations on both sides. Disbursal is the third, and it is milestone-linked, meaning money follows verified progress rather than preceding it. A project can hold stage one and never reach stage three, which is exactly why a Cabinet nod should never be reported as a factory.
The scheme is also not a single fixed thing. As of December 2025, ten ISM projects had been approved across six states DURABLE. ISM 2.0, announced in the Union Budget for 2026-27, shifts emphasis towards semiconductor equipment and materials manufacturing and full-stack Indian semiconductor intellectual property DURABLE, which is a recognition that a fab without a domestic supply chain around it stays an import-assembly operation. At Dholera specifically, the Union Cabinet approved Crystal Matrix Limited on 5 May 2026 for an integrated compound semiconductor fab covering Mini and Micro-LED display panels and RGB Mini and Micro-LED GaN epitaxy wafers DURABLE, which is an approval, not yet a build. Policy detail sits on the policy desk.
Which bars the Tata project has cleared, and which it has not
Set the four tests against the confirmed project and the picture is uneven but coherent. On technology, the PSMC transfer is signed and complete DURABLE, and Tata sent a couple of hundred people to PSMC in Taiwan for training, reported in batches of roughly seventy-five across equipment, yield, process technology and quality engineering REPORTED. On capital, the Cabinet approval, the Fiscal Support Agreement and the stacked Gujarat assistance are all documented DURABLE. On node choice, the plan is now openly a mature-first ramp, with commercial production publicly guided to mid-2028 by the union minister on 17 July 2026 TARGET. On customers, the project is weakest, and honesty requires saying so.
The physical evidence is the part that cannot be faked in a press release. A special economic zone for Tata Semiconductor Manufacturing Private Limited at Dholera was notified around 16 April 2026, covering 66.16 hectares DURABLE. Fugro, Cengrs and Geo Dynamics were engaged to redesign the main fab foundations after soil testing showed the ground unsuitable, reported on 28 November 2025 REPORTED, which is the sort of unglamorous engineering problem that surfaces once a specific site is being worked rather than described. Malaysia-based IAQ Group was onboarded to design and install the cleanroom REPORTED. INOX Air Products began construction in October 2025 on a Rs 500 crore electronic specialty gas hub at Dholera with a 200 tonne per day air separation unit DURABLE, because a fab cannot run without bulk and specialty gases delivered to purity on site.
Against that, no main engineering, procurement and construction contractor for the civil works has been publicly confirmed, no valued equipment purchase orders have been published, and claims that the site was fifty per cent complete in April 2026, or that foundations are finished, or that cleanroom installation is underway, appear only on real-estate and search-optimised sites with no primary source behind them DURABLE. The Tata Electronics file and the fab desk carry the running position.
The Micron and Sanand confusion, and why it keeps returning
Micron's Indian plant is at Sanand, not Dholera, and it is a back-end assembly, test and packaging facility rather than a wafer fab DURABLE. The two are different industrial activities. Front-end fabrication turns blank silicon wafers into patterned dies through hundreds of lithography, deposition, etch and implant steps in a cleanroom whose particulate and vibration specifications drive the entire building design. Back-end takes finished wafers, thins and singulates them, attaches dies to substrates, wire-bonds or bumps them, encapsulates, then tests. Back-end is capital intensive by ordinary standards and modest by fab standards, and it does not require a licensed process node at all.
The confusion persists because both sites are in Gujarat, both were approved under the same national push, and both are described in general coverage as "chip plants". It matters because conflating them inflates what Dholera has actually secured, and the same inflation mechanism is what keeps unconfirmed Vedanta claims circulating: a real fact from one place is quietly relocated to another, tiers are dropped, and an announcement becomes a factory in the retelling. This record separates the two on purpose, and will keep doing so.