Company file
Tata Electronics at Dholera
Published 3 August 2026. Facts verified to 27 July 2026 unless dated otherwise.
Tata Electronics and PSMC are building India's first commercial 300mm semiconductor fab at Dholera.
Tata Electronics, with Taiwan's PSMC as technology partner, is building India's first commercial 300mm semiconductor fab at Dholera: up to 50,000 wafers per month on 28 to 110 nm mature nodes. Union Cabinet approval came on 29 February 2024 under the India Semiconductor Mission and the Fiscal Support Agreement was signed on 5 March 2025. The plant is under construction.
Status tier: DURABLE
Why this one anchor changes the whole story
Cities on paper attract announcements. Construction sites attract suppliers. The Tata fab is the difference between the two for Dholera: a Rs 91,000 crore plant that is physically being built, with a signed fiscal support agreement, a notified SEZ and a global equipment maker at the table. Almost every other line in the capital ledger exists because this one does.
The verified record
- Approval: Union Cabinet, 29 February 2024, under the India Semiconductor Mission. DURABLE
- Fiscal Support Agreement: signed 5 March 2025. DURABLE
- Capacity: up to 50,000 wafers per month, mature nodes 28 to 110 nm. DURABLE
- SEZ: Tata Semiconductor SEZ notified around April 2026 on 66.16 hectares, with about 21,000 jobs cited (Business Standard, Times of India). DURABLE
- Technology partner: PSMC (Powerchip), Taiwan. DURABLE
- Equipment: ASML lithography MoU with Tata Electronics, announced 16 May 2026 by both the ASML and Tata Electronics newsrooms. REPORTED
- First silicon: guided to mid-2028. TARGET
- Commercial production: targeted mid 2028. TARGET
What to watch next
Two dates decide the next chapter: the mid-2028 commercial-production guidance, and the ramp toward commercial output in 2028. Both are targets, and this ledger will score them on the promise vs delivery page when they land, either way.
The corporate structure behind the fab
Tata Electronics Private Limited is the group's electronics manufacturing arm, and it is the entity that signs the technology and equipment agreements. The fab itself sits under a separate vehicle, Tata Semiconductor Manufacturing Private Limited, the name that appears on the Special Economic Zone notification issued by the Union Ministry of Commerce and Industry for the Dholera site DURABLE. The distinction is not cosmetic. Large process plants are almost always built inside a ring-fenced project company, because that is what lets a lender take security over a defined asset base, lets fiscal support be disbursed against a defined capital account rather than a parent's consolidated spending, and lets an SEZ attach to a named unit.
Randhir Thakur is chief executive and managing director of Tata Electronics DURABLE. Beyond that, the shareholding split, the debt structure and the internal allocation of the Rs 91,000 crore DURABLE between land, shell, cleanroom, utilities and tools are not in any primary document we have seen. Anyone offering a line-item capital breakdown is estimating. Separately, and worth repeating: Micron's Indian plant is at Sanand, not Dholera, and it is a back-end assembly and test facility, not a wafer fab DURABLE.
The instrument chain, and what each document actually does
Three instruments carry this project, and they do different work. Union Cabinet approval on 29 February 2024 DURABLE was a policy decision: it admitted the project to the India Semiconductor Mission and established the principle of central support. It did not move money. The Fiscal Support Agreement signed on 5 March 2025 DURABLE is the operative contract, under which the Government of India committed fifty per cent fiscal support. The twelve months between them says something about how long it takes to convert an approved scheme into agreed drawdown conditions and audit mechanics. Support of this type is normally reimbursed against verified capital expenditure rather than paid in advance, so the sponsor funds first and claims after.
The SEZ notification, issued around 16 April 2026 over 66.16 hectares DURABLE, is the most operationally useful of the three. A wafer fab is one of the most import-intensive facilities anyone builds: tools, spares, precursors, photoresists and specialty gases are overwhelmingly sourced abroad, and a serious cash-flow and schedule risk during fit-out is duty and clearance friction on hundreds of scheduled shipments. SEZ status treats the unit as outside the customs territory for authorised operations, removing that friction where it bites hardest.
Stacked on top is Gujarat's Semiconductor Policy 2022 to 2027 DURABLE: forty per cent of the centre's approved capital assistance, a seventy-five per cent land subsidy on the first 200 acres in Dholera Semicon City and fifty per cent on additional land, water at Rs 12 per cubic metre for five years and rising ten per cent a year thereafter, Rs 2 per unit off power for ten years with an electricity duty exemption, and a fifty per cent capital subsidy on a desalination plant built within the first five years DURABLE. The package targets the two inputs a fab consumes without limit. See the policy guide and SEZ guide.
What 50,000 wafer starts a month actually means
The headline capacity is up to 50,000 wafer starts per month on 300mm wafers DURABLE. "Starts" is not "outs": a wafer start is a wafer entering the line, and it will be roughly four to eleven weeks before it leaves, because mature CMOS flows run on the order of one to two days per mask layer including queue time and can carry twenty-five to forty layers. A fab at 50,000 starts therefore holds on the order of a hundred thousand wafers in process at any moment: working capital and risk on the floor. "Up to" describes the design capacity of the completed facility, not a day-one number.
The output arithmetic is worth doing once. A 300mm wafer carries roughly 70,700 square millimetres of surface, a few per cent of it lost to edge exclusion. A power management IC or small microcontroller die is often 5 to 25 square millimetres, so one wafer yields of the order of three thousand to thirteen thousand gross die. At 50,000 wafers a month, a fully ramped plant of that shape is sized in the billions of chips a year gross, before yield loss and test rejects. Power management ICs and microcontrollers, the products Tata's own foundry material names DURABLE, are exactly the high-volume, long-lifecycle, low-die-cost parts that justify capacity at that scale, and parts where a qualified supply relationship tends to last a decade.
How a fab ramps to nameplate
Nameplate capacity describes the finished building, not year one. Fabs are built shell-first and tooled in modules, because equipment is the dominant share of the capital and no sponsor buys 50,000 wafers a month of tooling before a lot has run. The sequence is shell and utilities, cleanroom fit-out, tool move-in and hook-up, qualification tool by tool, then a climb through engineering lots, risk production, qualification lots and volume. The gates are statistical, not calendar-based: defect density has to come down a learning curve before yields support commercial pricing, and that curve is walked one split lot at a time.
Customer qualification adds a second clock. A foundry cannot sell a wafer until the customer has qualified the process for their own part, and in automotive and industrial markets that means AEC-Q100 stress testing, production part approval and IATF 16949 audits, measured in quarters. This is why the gap between first silicon and meaningful revenue is routinely a year or more, and why the mid-2028 commercial production guidance TARGET reads as the start of a ramp rather than the moment the plant reaches 50,000. Our fab schedule risk file sets out the failure modes by frequency.
The node question, and why 90nm is not a downgrade
Bloomberg reported on 17 July 2026, carried in India by Outlook Business, that the fab will open mostly at 90nm rather than 28nm, with commercial production in mid-2028 REPORTED. TrendForce confirmed the account on 20 July 2026 REPORTED. A Tata spokesperson said the plan "has always been to start with 55nm and 90nm before introducing 28nm" REPORTED, and PSMC's Eric Tang noted that transfers are "typically introduced gradually, starting with more mature nodes" REPORTED. Against that sits N Chandrasekaran's line in the Tata Sons annual report for the year ended March 2025: "We have chosen to start our chip journey at the 28nm node" REPORTED. Both are on the record. They do not reconcile, and we will not pretend they do.
On the engineering, the sequencing is orthodox. 28nm and 90nm are not two settings on a dial. They are different lithography strategies, with 28nm critical layers generally requiring 193nm immersion scanners while 90nm can be served by dry 193nm and 248nm tools; they carry very different mask counts and therefore different cost per wafer; and 28nm platforms commonly offer a high-k metal gate option with no 90nm equivalent, although poly and SiON variants of 28nm also exist. A fab building a workforce that is largely new to volume production learns faster on a more forgiving process. The node range officially cited, 28, 40, 55, 90 and 110nm DURABLE, repeated in the ASML announcement REPORTED, was always a range rather than a starting point.
What is missing is the number that would settle it: how much of the 50,000 wafer starts is 28nm-capable at steady state, and when. That has not been published. No first silicon has been reported as of 4 August 2026 DURABLE, and the older "first chip by December 2026" figure traces to ministerial statements rather than any company document REPORTED. See the node question file and why mature nodes.
The partner list, sorted by what is actually committed
The partner announcements are not equivalent, and the difference matters more than the logos.
- PSMC is the only one that is structurally load-bearing. The technology transfer agreement was completed on 26 September 2024 DURABLE, and DigiTimes reported in January 2025 that PSMC expects more than NT$20 billion, roughly US$620 million, from consulting, technology transfer and training across the lifecycle REPORTED. That is revenue on PSMC's side and, on Tata's side, a cost that sits somewhere inside the Rs 91,000 crore DURABLE, though the split has not been published. What is on the record is a sale of process, service and people; no output-sharing or equity arrangement has been disclosed either way.
- ASML signed a memorandum of understanding announced on 16 May 2026 by both the ASML press release and the Tata Electronics newsroom REPORTED, with Randhir Thakur quoted on a timely ramp. Dual publication makes it real as an intent, but it is not a purchase order and books no scanner slots. Litho tools carry long lead times, so the signal that matters is a dated order. See the ASML file.
- INOX Air Products is arguably the most durable line here, because it is construction rather than paper: work began in October 2025 on a Rs 500 crore electronic specialty gas hub at Dholera including a 200 tonne-per-day air separation unit DURABLE. A fab consumes bulk nitrogen continuously at purity levels that make road tankering impractical at scale, so an over-the-fence air separation unit is the classic tied investment: long payback, built around an anchor customer, and therefore a real vote on the fab reaching production. See gases and chemicals.
- Intel signed an explicitly non-binding exploratory MoU on 8 December 2025 to explore manufacturing and packaging of Intel products REPORTED. The words non-binding were in the announcement and should stay attached to the claim.
- Qualcomm announced a partnership on 20 February 2026 for automotive modules in India REPORTED, scope and any Dholera link unverified. ROHM announced a strategic partnership on 22 December 2025 REPORTED, scope unverified. Fujifilm signed an MoU with the Gujarat State Electronics Mission on 30 June 2026 to explore a semiconductor materials base REPORTED. Linde is reported by gasworld to be advancing plans for a Dholera plant REPORTED, held at low confidence. The partner ledger tracks these.
The training pipeline, and the number missing from it
Technology transfer in semiconductors is mostly a people transfer. Recipes travel in documents; the ability to hold a process inside its control limits travels in engineers who have watched one drift. Tata sent what the Economic Times described in June 2025 as a couple of hundred people to PSMC in Taiwan REPORTED, reported as batches of around seventy-five covering equipment, yield, process technology and quality engineering REPORTED. Those four disciplines map onto the four things that break new fabs: tool uptime, defect density, recipe control and outgoing quality.
The scale needs honest framing. A 300mm fab at 50,000 wafer starts a month runs continuously across multiple shift crews and is typically staffed in the low thousands of direct roles. A couple of hundred people trained abroad is seed corn: module owners and shift leads who then train the next cohorts on site. That is the standard model, but it means the local training pipeline, not the Taiwan trips, is the binding constraint on ramp speed. Reporting around the SEZ notification cites about 21,000 jobs REPORTED and Tata's own 2024 release cites 20,000 or more direct and indirect DURABLE; neither is a published fab payroll figure. Our jobs answer separates the two.
The build side, the negative findings, and what to watch
Two construction facts are sourced. In November 2025 the Economic Times reported that Fugro, Cengrs and Geo Dynamics had been engaged to redesign the main fab foundations after soil testing showed the ground unsuitable REPORTED. That is more significant than it reads. Lithography tools hold overlay budgets measured in nanometres, so fab floors are designed to vibration criteria far tighter than ordinary industrial slabs, usually a thick isolated mat on improved or piled ground. Weak or compressible ground pushes a design towards deeper foundations or ground improvement, adding cost and, more importantly, sequence time before any superstructure rises. The specific soil parameters behind the redesign have not been published; the report says only that the ground was found unsuitable. In June 2026 ETtech reported that the Malaysia-based IAQ Group had been onboarded to design and install the cleanroom REPORTED, consistent with a fit-out phase beginning rather than concluding. See cleanroom engineering and the foundation redesign file.
The negative findings matter as much as the positive ones. There is no publicly confirmed main EPC or civil contractor, and no publicly valued equipment purchase orders. Claims that the project was "fifty per cent complete" in April 2026, that foundations are complete, or that cleanroom installation is underway appear only on real-estate and search-optimised sites with no primary source, and we do not carry them at any tier. Contracts of this size are often confidential, so absence of publication is not proof of absence. It does mean nobody outside the project can currently verify physical progress, and the unverified claims file lists what is circulating.
The signals that would move this record, in rough order of value: a named main EPC or civil contractor; a dated, valued equipment order converting the ASML MoU into scanner slots; a cleanroom classification handover or first tool move-in from a primary source; a disclosure of how much of the 50,000 wafer starts is 28nm-capable and when; commissioning of the INOX air separation unit; bulk water, where a tender was issued on 9 July 2026 to appoint consultants for a 200 MLD desalination plant DURABLE against roughly 20 MLD today DURABLE; the balance 700 MW of the Dholera solar park against its March 2027 target TARGET; a first named customer qualification; and whether the mid-2028 guidance TARGET survives the next annual report. Each is checkable and scoreable on the promise versus delivery page.