Guide
The Tata + PSMC partnership: who brings what to India's first fab
Published 3 August 2026. Facts verified to 27 July 2026 unless dated otherwise.
No nation has bootstrapped commercial semiconductor manufacturing alone since the industry globalised. The interesting question about Dholera was never whether Tata had a partner, but what the partnership actually transfers.
What this page establishes
- The division of labour
- Why Powerchip specifically makes sense
- What technology transfer actually means here
- The honest risk register
- The one-line version
Tata Electronics (TEPL, established 2020) owns and builds the Dholera fab; PSMC, Taiwan's Powerchip Semiconductor Manufacturing Corporation, is the technology partner contributing 300mm process technology for the 28 to 110 nm node range.
The division of labour
Tata Electronics brings the balance sheet, the site, the Indian operating environment and the group's century of industrial execution; the Rs 91,000 crore commitment and the Fiscal Support Agreement sit on its side of the table DURABLE. PSMC brings what cannot be bought off a shelf: qualified 300mm process flows in the mature-node range, the yield-learning playbook, and the operational muscle memory of running high-volume fabs in Taiwan, the industry's deepest talent pool. A fab is less a building than a choreography, and the choreography is the import.
Why Powerchip specifically makes sense
PSMC's business is exactly the segment Dholera targets: mature-node foundry work, the 28 to 110 nm range that powers automotive, industrial, display and power-management silicon DURABLE on the node range. A leading-edge partner would have been the wrong teacher for this curriculum; the mature nodes guide explains why the curriculum itself is the right one for a first fab. The partnership's shape also fits Taiwan's broader posture of diversifying manufacturing geography without transferring its crown-jewel leading edge, which is why mature-node partnerships travel while 3-nanometre ones do not.
What technology transfer actually means here
- Process recipes: the validated step-by-step flows for each node, the difference between owning tools and getting yield from them.
- Ramp discipline: the sequence from first wafers through yield learning to the commercial-production guidance of mid-2028 TARGET, where most greenfield fabs bleed.
- People pipelines: training rotations and expatriate supervision during ramp; the careers guide reads the employment side of this.
- Supplier qualification: the audit standards that let a new site's gases, chemicals and materials, the layer forming via INOX REPORTED and Fujifilm's exploration REPORTED, be certified for production use.
The honest risk register
Partnerships of this kind carry known failure modes: knowledge transfer that stays shallower than press releases suggest, ramp timelines that assume Taiwanese supplier density which India does not yet have, and the governance friction of a first-of-kind project under national spotlight. Against them stand the visible commitments: Cabinet money DURABLE, a notified SEZ DURABLE, an ASML engagement REPORTED and physical construction. This record does not adjudicate the invisible; it tracks the visible on the promise vs delivery ledger and lets delivery testify.
The one-line version
Tata is buying time, the decade it would take to learn fab operations alone, and PSMC is selling it, in a segment where its expertise is exactly on-syllabus. Whether the purchase works will be visible in two numbers nobody can spin: the date of first silicon, and the slope of yield after it. Both will be on this record the week they are knowable.
What a process technology transfer actually hands over
The phrase "technology transfer" flatters the transaction. What moves between a foundry licensor and a licensee is not a single artefact but a library, and most of it is deeply unglamorous. The core deliverable is the process flow: an ordered list of several hundred to well over a thousand individual steps, each specifying a tool type, a chamber configuration, a chemistry, a temperature, a duration, a pressure, and an acceptance window. Around that sit the recipe files themselves, the run cards that tell operators and automation what to do at each stage, the metrology plan that decides which lots get measured and where, and the statistical process control limits that define when a chamber is considered out of family and pulled from production.
Alongside the manufacturing flow travels the design-enablement package, which is what actually makes a foundry sellable. That means the process design kit, the extracted SPICE models for every transistor flavour and every corner, the design rule manual, the design rule checking and layout-versus-schematic decks, standard cell and I/O libraries, memory compilers, and the certification work that makes all of it run inside commercial EDA tools. A fab that can make wafers but cannot hand a customer a qualified PDK is not a foundry, it is a job shop. The Tata and PSMC technology transfer agreement was completed on 26 September 2024 DURABLE, and that date should be read as the start of a multi-year porting exercise rather than a handover of finished goods.
The third component is qualification: the reliability protocols that convert a working wafer into a part a customer will design into a product. High temperature operating life, temperature cycling, highly accelerated stress testing, electromigration and time-dependent dielectric breakdown characterisation, plus the automotive-grade regimes that power management and microcontroller customers demand. These take real calendar time and cannot be compressed by capital.
The economics on the Taiwanese side of the table
Powerchip's incentive structure is worth reading plainly, because it explains a great deal about pacing. DigiTimes reported in January 2025 that PSMC expects more than NT$20 billion, roughly US$620 million, from consulting, technology transfer and training across the lifecycle of the engagement REPORTED. Set against a project capitalised at Rs 91,000 crore, about US$11 billion, approved by the Union Cabinet on 29 February 2024 DURABLE, that is somewhere near five to six per cent of headline project cost. Nothing in the public record describes PSMC taking an equity position in the Dholera fab; what has been disclosed is compensation for consulting, technology transfer and training REPORTED, which reads as a service annuity rather than an equity bet.
That distinction matters, if it holds. A licensor paid in milestones and consulting hours is compensated for effort and elapsed time. A licensor holding equity is compensated for output. The two structures pull schedules in different directions when yield turns out to be harder than planned. Nothing in the public record suggests PSMC has behaved opportunistically, and there is no reason to assume it, but the shape of the contract is something any reader assessing ramp promises should hold in view. It also explains why a mature-node licensor with spare engineering capacity finds this kind of work attractive: the marginal cost of exporting a process it has already amortised is close to the cost of the people it seconds.
The Fiscal Support Agreement signed on 5 March 2025 DURABLE commits the Government of India to fifty per cent fiscal support for the project DURABLE, with Gujarat's 2022 to 2027 semiconductor policy layering a further forty per cent of the centrally approved capex assistance on top DURABLE. Subsidy of that magnitude changes the internal rate of return arithmetic but does not change the operating economics of a mature-node fab, where gross margin is a function of tool utilisation, yield and product mix. The stated design capacity is 300mm wafers at up to fifty thousand wafer starts per month DURABLE, which would be a large mature-node position by any measure, and filling it is a commercial problem that no capital subsidy solves.
Training rotations and the part of the process that is not written down
The Economic Times reported in June 2025 that Tata had sent "a couple of hundred" people to PSMC in Taiwan REPORTED, with reported batch sizes of roughly seventy-five spanning equipment, yield, process technology and quality engineering REPORTED. Those four disciplines are a sensible spread, and the batching is not arbitrary. A receiving fab cannot absorb a whole cohort at once, and a sending fab cannot host one without disrupting its own production.
The reason people travel at all is that a large fraction of process knowledge is tacit. A recipe file will tell an engineer the deposition time. It will not tell them that a particular chamber drifts after a specific number of runs, that a certain preventive maintenance sequence must be performed in a particular order to avoid a first-wafer effect, or how a seasoned technician reads a subtle signature in a defect map and knows immediately which of three tools to suspect. That knowledge lives in people and moves at the speed of apprenticeship. It is why the industry's most disciplined operators have historically insisted on replicating a reference fab as exactly as possible, down to tool vendors and chamber revisions, rather than substituting equivalents.
Attrition is the quiet threat here. Engineers trained on a working 300mm flow become internationally marketable, and a fab that is still years from commercial production, guided at mid-2028 TARGET, has to retain them through a long period with no product to show. Retention through a pre-revenue ramp is a management problem with no elegant solution, and no public information exists on how many of the returning cohort remain in place.
Why mature nodes go first, and why the chairman said otherwise
The gradual introduction of nodes is standard industrial practice, and PSMC's Eric Tang described it exactly that way when he said transfers are "typically introduced gradually, starting with more mature nodes" REPORTED. The logic is operational. Every fab has to learn its own defect signature: its water, its air, its gas purity, its people, its handling, its vibration environment. A mature flow with fewer mask layers, looser overlay budgets and wider process windows is a far more forgiving instrument for that learning, because the yield loss is easier to attribute. Trying to debug a fab and a tight process simultaneously means never knowing which one caused a given failure.
Bloomberg reported on 17 July 2026, carried in India by Outlook Business, that the fab would open mostly at 90nm rather than 28nm, with commercial production in mid-2028 REPORTED, and TrendForce corroborated the reporting on 20 July 2026 REPORTED. A Tata spokesperson responded that the plan "has always been to start with 55nm and 90nm before introducing 28nm" REPORTED.
The difficulty is that Tata Sons chairman N Chandrasekaran wrote in the annual report for the year ended March 2025 that "We have chosen to start our chip journey at the 28nm node" DURABLE. Both statements cannot be casually reconciled. Either the plan changed between the annual report and July 2026, or the annual report described the destination while operations described the sequence, or the phrase "start our chip journey" was intended to signal ambition rather than first-wafer configuration. The honest position is that the public record contains a contradiction that has not been formally resolved, and readers should treat any single quoted node as a claim about intent rather than about what will run through the tools first.
What 28nm demands that 90nm does not
The gap between the two nodes is larger than the arithmetic suggests. At 90nm and 110nm, many layers can be patterned with krypton fluoride steppers at 248nm exposure wavelength, with argon fluoride at 193nm reserved for the tightest features. At 28nm, the critical layers require immersion lithography, where a water film between the final lens element and the wafer raises the effective numerical aperture. Immersion tools are more expensive, slower to qualify, and introduce their own defect mechanisms involving watermarks and bubbles. The ASML memorandum of understanding announced on 16 May 2026 by both ASML and Tata Electronics named the full 28, 40, 55, 90 and 110nm range DURABLE, which is consistent with a toolset intended to cover the whole span rather than one point on it.
Beyond lithography, 28nm brings materially more mask layers, tighter overlay and critical dimension uniformity budgets, and, in its high-performance variants, high-k metal gate integration with chemical mechanical planarisation steps that have narrow windows and unforgiving failure modes. It also brings a harder design-enablement burden, since customers at 28nm expect mature libraries, memory compilers and silicon-validated IP. Power management integrated circuits and microcontrollers, the products named on Tata's own foundry page DURABLE, do not generally require 28nm. Analogue and high-voltage content scales badly, and many power management parts are economically better served at 180nm or above. The node question is therefore also a product question, and the two have not been publicly mapped to each other.
Precedents: how fab technology partnerships have gone before
The pattern is old enough to have a track record. TSMC itself began with process technology contributed by Philips as a founding shareholder, which shortened its path to a working flow considerably. Samsung's entry into memory in the early 1980s combined licensed designs and external process assistance with an unusually aggressive internal learning programme, and the internal programme, not the licence, is what produced the eventual lead. Chartered Semiconductor in Singapore ran licensed IBM processes for years through the Common Platform arrangement, and demonstrated both that a licensee can reach production and that a licensee tends to remain a node or more behind the licensor.
Three lessons repeat. First, licensing reliably compresses the time to a working process and reliably does not compress the time to competitive yield, which the licensee has to earn on its own equipment. Second, the partnerships that worked were the ones where the licensee built genuine internal process integration capability rather than treating the licensor as a permanent supplier, because the licence covers the node you bought and not the node after it. Third, the failures were rarely technical. The Vedanta and Foxconn joint venture collapsed in 2023 after Foxconn's exit DURABLE, which points to the more common failure mode: partner selection and financing, not physics.
The risk register
Set out honestly, the exposures fall into five groups.
- Schedule and civil works. The Economic Times reported on 28 November 2025 that Fugro, Cengrs and Geo Dynamics were engaged to redesign the main fab foundations after soil testing found the ground unsuitable REPORTED. This is a serious item rather than a routine one. Lithography tools require very quiet vibration environments, commonly specified in single-digit microns per second of velocity or lower, which on ground that has tested unsuitable typically means deep piling and very stiff mat slabs. Foundation redesign lands on the critical path because nothing above it can proceed. There is still no publicly confirmed main civil or EPC contractor REPORTED, and no publicly valued equipment purchase orders REPORTED, which are the two disclosures that would let an outsider verify a ramp date independently.
- Yield and qualification. Each yield learning cycle takes as long as the line's cycle time, typically several weeks for a mature logic flow, and customer qualification for automotive or industrial parts adds further quarters after first good silicon. Guidance of mid-2028 for commercial production TARGET should be read as the start of that clock, not the end of it. No first silicon has been publicly reported REPORTED.
- Market. Global mature-node capacity has been expanding rapidly, particularly in China, and the 90nm to 55nm band sits inside the range where that competition is most intense. A fab that arrives late into an oversupplied segment competes on price, and price competition against fully depreciated lines is unpleasant.
- Dependency. A single-source technology relationship concentrates both commercial and geopolitical risk in one counterparty in one jurisdiction. The mitigation is internal capability, and internal capability is exactly what takes the longest to build.
- Utilities and supply chain. INOX Air Products began construction in October 2025 on a Rs 500 crore electronic specialty gas hub at Dholera with a 200 tonne per day air separation unit DURABLE, which addresses bulk gases. Ultrapure water at fab specification, uninterrupted power quality, and the long tail of photoresists, precursors and targets remain the harder items. A tender was issued on 9 July 2026 to appoint consultants for a 200 MLD seawater desalination plant REPORTED, which is a consultant appointment rather than a plant.
None of these is disqualifying. Taken together they explain why the interval between a signed technology transfer and a shipped wafer is measured in years, and why the most useful thing to watch is not node announcements but the arrival of unglamorous disclosures: a named civil contractor, a valued tool order, and a customer qualification.
Sources and verification trail
- Dholera knowledge base fact pack, verified to 27 July 2026.
- Dholera Digital capital ledger, August 2026 edition (dholera.digital/data/capital-ledger/).
- Dholera Digital key numbers, verified 27 July 2026 (dholera.digital/data/key-numbers/).
- Primary and reputable sources named inline on this page, each with its date.
- Verification method: dholera.digital/editorial-standards/