The answer desk
Will Indian fabs make AI chips?
Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.
Not the accelerators, and not soon. Every manufacturing unit approved in India to date is built for mature silicon, compound semiconductors or packaging, and the training chips that people mean by AI chips are made at leading-edge nodes with tooling and packaging India has not yet approved. What Indian plants will make is the support silicon that sits around accelerators, including power management chips and microcontrollers. Indian design teams already design for AI systems and have them fabricated abroad.
The answer, and the two words carrying it
Asked plainly, will Indian fabs make AI chips, the accurate answer as of 25 August 2026 is no, not the chips that the question usually means, and not on any approved project. That answer turns on what the questioner intends by AI chip. If the term means the accelerators used to train and serve large models, then nothing in India's approved manufacturing portfolio is designed to make one. If the term means any silicon that appears inside an artificial intelligence system, then India's plants will make a good deal of it, and that adjacency is real rather than a consolation prize.
The confusion is worth taking seriously because it is not confined to social media. Announcements about data centres, design startups and fab construction get compressed into a single national story in which India is about to make AI chips, and each of those three things is a different industry with a different timeline. This page separates them.
What an AI accelerator actually requires
Standard semiconductor manufacturing practice sets the bar here, and the bar is high in three separate places at once. The logic die of a modern training accelerator is fabricated at a leading-edge node, which today means processes in the low single-digit nanometre class, patterned with extreme ultraviolet lithography. That tooling is available from one supplier in the world and is not part of any Indian project's disclosed tool plan. The partnership that Tata Electronics and ASML announced on 16 May 2026 names nodes of 28, 40, 55, 90 and 110 nanometres DURABLE, which is deep ultraviolet territory by design, and the reasoning behind that choice is set out at mature node products.
The second requirement is memory bandwidth. Accelerators are paired with stacked high-bandwidth memory, which is manufactured by a very small number of memory makers and requires through-silicon vias and precise stacking. No memory fabrication plant appears anywhere in India's approved portfolio, and none is operating in the country.
The third requirement is advanced packaging, and it is the one that most often decides how many accelerators the world can actually build in a given quarter. Putting a large logic die and several memory stacks onto a silicon interposer is a manufacturing discipline in its own right, described at advanced packaging. India's approved packaging units are conventional assembly and test operations. That is not this desk's characterisation: the Cabinet decision on the next programme phase, announced on 15 July 2026, states as one of its own six pillars the aim of getting some of the most advanced assembly and test technologies to India, which is an official acknowledgement that they are not here yet.
What India's approved plants are actually built to make
The portfolio is public and specific. As recorded in the Press Information Bureau's Cabinet release of 15 July 2026, twelve manufacturing units have been approved with cumulative investment of over Rs 1.64 lakh crore, comprising one silicon fab, one silicon carbide fab, one integrated gallium nitride micro LED display fab and nine packaging units DURABLE. Three of the twelve, Micron, Kaynes and CG Semi, had started commercial production by that date, with one more expected to begin during 2026.
Read that list against the accelerator requirements above and the answer resolves itself. The one silicon fab is the Dholera plant, whose stated node range runs from 28 to 110 nanometres, with reporting by Bloomberg on 17 July 2026 and TrendForce on 20 July 2026 indicating that it opens mostly at 90 nanometres REPORTED, while the Tata Sons chairman's letter in the FY25 annual report described a start at 28 nanometres. This record does not resolve that contradiction, it prints it. The silicon carbide fab serves power electronics, a genuinely important market that has nothing to do with matrix multiplication. The gallium nitride unit is aimed at micro LED display panels and epitaxy wafers. The nine packaging units are the back-end layer. Not one of those descriptions is an accelerator line, and none of them claims to be.
The support silicon, which is the honest adjacency
An artificial intelligence system is not only accelerators. A rack of them is surrounded by power delivery hardware, and power delivery is built from exactly the sort of silicon a mature-node fab exists to make: power management integrated circuits, voltage regulation, discrete power devices, sensors and the microcontrollers that supervise a chassis. The approval record for the Dholera fab names power management chips, display drivers, microcontrollers and high performance compute logic among its intended products DURABLE, and the product-set question takes that list apart in detail.
Two honest limits belong with that observation. The first is that support silicon is a lower-value slice of the system than the accelerator, so participating in the AI build-out through power management is participation on modest commercial terms. The second is that no customer relationship of this kind has been announced for any Indian plant, so the adjacency described here is a market structure argument, not a contract. This desk has seen no public evidence of an Indian-made chip being qualified into an artificial intelligence system, and will say so plainly until such evidence exists.
Design is already here, manufacturing is not
The most commonly misread evidence in this debate comes from the design side, where India genuinely has depth. The same Cabinet release of 15 July 2026 records that twenty-four semiconductor design projects from startups and small enterprises have been approved for financial support, and that 105 startups and small enterprises have been granted access to industry-standard electronic design automation tools, designing chips and systems on chip for applications including satellite communications, drones, surveillance cameras, internet of things devices, LED drivers, telecom equipment, smart meters and artificial intelligence systems DURABLE.
That last phrase is the one that gets quoted. It is accurate and it does not say what it is often taken to say. Designing a chip for an AI system is a design activity, and the resulting design must then be fabricated somewhere. The Press Information Bureau backgrounder of 7 February 2026 is explicit about where: startups under the design-linked incentive had completed sixteen tape-outs, resulting in six chips fabricated at advanced foundry nodes including technologies as advanced as 12 nanometres DURABLE, which is to say at foundries outside India, because no Indian line runs those processes. On the academic side, 122 designs had been taped out with fifty-six chips fabricated at 180 nanometres at the Semiconductor Laboratory in Mohali.
India therefore designs at nodes it cannot manufacture, and manufactures at nodes it mostly does not need to import designs for. Closing that gap is the actual project, and it is a decade-scale one. The design layer's own economics are covered at the chip design industry in India.
A data centre is not a fab
The third source of confusion is geographic, and it lands directly on the ground this record covers. Dholera is being pitched simultaneously as a fab location and as a data centre location, and the two propositions travel together in headlines until readers conclude that the chips in the data centre will come from the fab next door. They will not. A data centre is a customer for accelerators, bought on a global market whose supply base is heavily concentrated: the Press Information Bureau's backgrounder of 7 February 2026 records that Taiwan alone produces over 60 percent of the world's semiconductors and nearly 90 percent of the most advanced ones. A mature-node fab is a supplier of other kinds of silicon. The two are neighbours, not a supply chain.
The largest such plan on the record here is the L and T Vyoma agreement for an artificial intelligence data centre at Dholera, reported by the government's own news service on 20 February 2026 at Rs 25,000 crore and 250 megawatts, with an operational target around 2028 REPORTED on the figures, which are agreement-stage rather than commissioned capacity. The data centre hub guide tracks that layer. If both projects deliver, Dholera will host a plant that makes mature-node chips and a facility that consumes advanced ones, which is an interesting industrial cluster and still not a domestic AI chip.
The edge inference exception, stated carefully
One nuance rescues this answer from being flatly negative, and it deserves a section rather than a footnote. Not all silicon that performs artificial intelligence work is leading-edge silicon. Training a large model demands the extremes described above, but a great deal of inference happens away from the data centre, inside cameras, meters, vehicles, appliances, industrial controllers and handsets, on parts that are small, cheap and power-constrained. Neural processing blocks of that kind are routinely integrated into microcontrollers and application processors at mature nodes, because the design constraint at the edge is milliwatts and unit cost rather than raw throughput. That is standard practice in the industry rather than a claim about any Indian project.
The relevance here is arithmetic. The Dholera fab's stated range reaches down to 28 nanometres, and 28 nanometres is a node at which edge inference parts, sensor processors and smart-metering chips are made all over the world today. If the plant reaches the lower end of its range, edge-class parts sit inside its technical envelope. That is a statement about physics and process capability, not about intent.
What is missing is every commercial fact that would matter. No product roadmap for the plant has been published beyond the broad category list in the approval record, no customer has been named, and the reporting on the opening node points to 90 nanometres rather than 28 REPORTED, which places the fab's first output well above the range where edge inference parts are usually made. So the correct formulation is narrow and this desk will hold to it: an Indian mature-node fab could plausibly make edge inference silicon at some future point in its ramp, nobody has announced that it will, and anyone converting that possibility into a headline about India making AI chips has skipped the only steps that count.
The stated ambition, and how this desk will score it
Intent exists and it is on the record. The fifth pillar of the phase approved on 15 July 2026 states that the semiconductor journey has started at 28 to 110 nanometres and that the focus will now be on developing more advanced nodes and other advanced technologies in collaboration with leading research centres in India and abroad DURABLE. The backgrounder of 7 February 2026 goes further, describing a roadmap toward 3 nanometre and 2 nanometre technology nodes, a capability to design and manufacture chips for nearly 70 to 75 percent of domestic applications by 2029, and an ambition to rank among the top semiconductor nations by 2035 TARGET.
Those are targets, and this record scores targets rather than arguing with them. The interesting feature of the 2029 formulation is that it is about domestic applications rather than about node leadership, and most domestic applications by unit volume do not need leading-edge silicon. A country can serve three quarters of its own chip demand without ever fabricating an accelerator. Whether the more advanced node ambition converts into anything is a separate question, examined at will India make advanced chips.
What would change the answer
Four developments would move this page from no to something else, and none of them has occurred. An approved project at a node below 28 nanometres, which would require an extreme ultraviolet tool plan and a technology partner willing to transfer such a process. A memory fabrication approval, since accelerators are bandwidth-bound and a domestic accelerator without domestic memory is a partial claim. An advanced packaging line capable of interposer-based integration, which the fourth pillar names as an objective rather than an achievement. And a disclosed customer qualification putting Indian-made silicon of any kind into an artificial intelligence system, which would at least convert the adjacency argument into a commercial fact. Until one of those appears in a primary document, the accurate answer to the question in the headline is the one this page opened with.
A reading habit helps in the meantime. When an announcement uses the phrase AI chip, look for the node, the wafer size and the packaging technology, because a claim that names none of the three is describing an ambition rather than a plant. Those three details are published for every serious project in this industry, and their absence is itself the finding.