The answer desk
What is a mature node in semiconductors?
Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.
A mature node is a chip manufacturing process that is no longer the industry's leading edge, has run in volume long enough for its yields and design rules to be well understood, and has largely paid off its tooling. In practice the industry draws the line at about 28 nanometres and above, which is also roughly where planar transistors give way to FinFET structures. The Dholera fab's stated range of 28 to 110 nanometres sits entirely inside mature territory, and so does the 90 nanometre start reported for it in July 2026.
The short definition, and the three tests behind it
A mature node is a semiconductor manufacturing process that has moved off the industry's leading edge, has been running in volume production long enough that its yields and design rules are well characterised, and whose equipment has largely been depreciated. The term is commercial as much as technical, which is why it resists a single clean threshold. Three tests are applied in practice, and a process is generally called mature when it passes all three.
- It is not the leading edge. Somebody else is making chips on a smaller, newer process for the products that need them. This test is relative and it moves: 90 nanometres was the leading edge in the mid 2000s and is deep legacy now.
- It is proven. The process has run at commercial yield for years, its design rules are stable, its process design kit is mature, and a designer can predict what will come back from the fab. This is the test that matters most to a customer.
- It is paid for. The tools were bought in an earlier capital cycle and have been depreciated, so the cost per wafer is dominated by materials, labour and utilities rather than by capital recovery. This is the test that matters most to the fab's owner.
A brand new fab built to run a mature process, which is exactly what is being built at Dholera, passes the first two tests and fails the third on day one. Its tools are new and unpaid for, so its cost per wafer starts well above that of a twenty year old line running the same node elsewhere. That is the central economic challenge of the project and it is worth stating plainly rather than hiding inside the word mature.
What a node name measures, and when it stopped measuring anything
Node names began as a physical measurement. Through the 1970s and into the 1990s, the number quoted for a process corresponded reasonably well to a real dimension on the chip, typically the gate length of a transistor or half the distance between repeating features. A 1 micron process really did have features of about a micron. Each generation shrank that dimension by roughly 0.7 times, which halved the area a given circuit occupied, and the industry got faster, cheaper and lower power chips at a predictable cadence.
Somewhere in the 2000s the correspondence broke. Manufacturers continued the naming cadence for marketing continuity while the physical dimensions stopped tracking it, so that by the time the industry reached the numbers now described as advanced, the node name had become a generation label rather than a measurement. Two companies quoting the same node number today may be building transistors of measurably different size and density. This is not a scandal, it is a convention, but it has one important consequence for a reader: a node number is a rough position on a timeline, not a specification. Comparing two processes properly requires transistor density, performance and power figures, not the headline number.
Above roughly 28 nanometres the naming is closer to honest, because those processes were named while the correspondence still broadly held. When this record writes that the Dholera fab's range is 28 to 110 nanometres, those numbers do map onto real generations of process technology with known characteristics, which is one reason mature node claims are easier to verify than advanced ones.
Where the line sits, and why the industry drew it there
There is no standards body that defines mature, and different sources place the boundary differently. The most common convention, and the one this record uses, treats 28 nanometres and above as mature. Some analysts draw the line at 16 or 14 nanometres and above, which sweeps in the first generation of FinFET processes. Some foundry reporting uses three bands: leading edge, mid range and mature, with the mature band starting somewhere between 40 and 28 nanometres.
The 28 nanometre convention has a real justification rather than an arbitrary one. It was the last widely deployed planar process generation, it remains in high volume production more than a decade after introduction, and it is the point below which the cost per transistor stopped falling reliably for many product types. That last point is the important one. For most of semiconductor history, moving to a smaller node made each transistor cheaper. Below 28 nanometres, the combination of multiple patterning, more masks and lower yields meant that for many designs the cost per transistor flattened or rose. A design that does not need the speed or power benefit of a smaller node therefore has no economic reason to move, and 28 nanometres became a resting point rather than a way station.
Planar and FinFET: the engineering break under the label
Underneath the commercial label sits a genuine engineering discontinuity, and understanding it makes the boundary intuitive. In a planar transistor, the gate sits above a flat channel and controls it from one side. As dimensions shrank, that single sided control became too weak: current leaked when the transistor was supposed to be off, and power consumption rose accordingly. The fix, introduced commercially at 22 nanometres and generalised below 16, was to stand the channel up as a fin and wrap the gate around three sides of it. That is the FinFET. Below roughly 3 nanometres the industry moved again, to gate all around structures where the gate surrounds the channel completely.
So the mature and advanced division is not only about size. It marks the point where transistor architecture changed, where lithography moved from single patterning to multiple patterning and eventually to extreme ultraviolet, and where the mask count and process step count rose sharply. A fab equipped for planar processes at 28 nanometres and above is a fundamentally different factory from one equipped for FinFET, in tooling, in cleanroom class requirements, in metrology and in the skills of the people who run it. This is why fabs do not simply upgrade downward through nodes, and why a mature node fab is a coherent long term business rather than a stepping stone that gets abandoned.
Why mature nodes did not go away
The expectation through the 2000s was that older processes would fade as production migrated to smaller ones. It did not happen, for four reasons that have held up.
First, a large share of the chips in any electronic system do not benefit from shrinking. Power management circuits handle voltages and currents that need physically larger structures. Analog and mixed signal blocks depend on device matching and noise behaviour that often get worse, not better, at smaller geometries. Radio frequency, sensing and high voltage functions have their own physical requirements. These functions cannot be shrunk into a leading edge process at any sensible cost, so they stay where they work.
Second, qualification is expensive and slow, particularly in automotive and industrial markets where a part may need to remain available and unchanged for ten to fifteen years. Once a design is qualified on a process, moving it costs a full requalification cycle, and the manufacturer needs a strong reason to pay for that.
Third, the economics described above stopped rewarding migration for many products. If the cost per transistor no longer falls, the case for a new mask set and a redesign evaporates.
Fourth, capacity begets products. A large installed base of mature capacity keeps prices competitive, which keeps designers targeting those nodes, which sustains demand for the capacity. The demand side of this argument, and the honest objections to it, are set out at why mature nodes, which this page is the definitional companion to.
What comes off a mature line
The products made at 28 to 110 nanometres are not exotic, which is exactly why they matter. Power management integrated circuits regulate voltage in every device with a battery or a plug. Display driver chips convert a video signal into the signals that address the pixels of a screen. Microcontrollers run appliances, motors, meters and vehicle subsystems. Analog and mixed signal parts convert between the physical world and the digital one. Discrete power devices switch current in chargers, drives and inverters. Sensor interface chips sit behind every camera, accelerometer and touchscreen.
A modern car contains hundreds of these and only a handful of parts that require an advanced node. The same is true of an industrial drive, a solar inverter, a router or a washing machine. It is also true, less obviously, of a data centre: the accelerators are made at the leading edge, but the power delivery, board management and interface silicon around them is mature node work. The product map for this category is developed further at mature node products.
Where Dholera sits on the map, precisely
The Tata Electronics fab at Dholera, built in technology partnership with Powerchip Semiconductor Manufacturing Corporation of Taiwan, is approved at a stated node range of 28 to 110 nanometres and a capacity of up to 50,000 wafer starts a month on 300 millimetre wafers, against an approved investment of Rs 91,526 crore, the figure listed for it in the annexure to a Lok Sabha reply published by the Press Information Bureau on 1 April 2026 DURABLE. Every node in that range is mature by any of the conventions above. The product set named in the approval record, power management chips, display drivers, microcontrollers and logic, is the standard mature node portfolio DURABLE.
Where inside the range the plant opens is genuinely disputed. Bloomberg reported on 17 July 2026 that it will open mostly at 90 nanometres rather than the 28 nanometres presented at approval, with TrendForce carrying the same finding on 20 July 2026, while the Tata Sons chairman's letter in the annual report for the 2025 financial year said the company had chosen to start at 28 nanometres REPORTED. This record documents the contradiction at the node question and does not resolve it, because no primary document does. The equipment agreement announced by both ASML and Tata Electronics on 16 May 2026 names 28, 40, 55, 90 and 110 nanometres, which is consistent with the full range and settles nothing about the opening node REPORTED. Commercial production is guided to mid-2028 TARGET, per the Union Minister for Electronics and Information Technology on 17 July 2026, and no supported first silicon date exists in the public record.
How to read node claims without being fooled
Four habits protect a reader in this subject. Treat the node number as a generation label, not a measurement, and ask for density or performance figures if a comparison is being made. Ask whether a quoted node is a capability the fab is equipped for or the node it will actually run in volume at opening, since those are different claims and the difference is where the Dholera dispute lives. Check whether a plant described as a fab actually fabricates wafers, because assembly, test, bumping and probe operations are routinely described with fab language and do not involve a node at all. And notice when mature is being used as a synonym for obsolete, which it is not: a mature process is one whose economics and yields are understood, and the majority of chips shipped worldwide come off exactly these lines.
A fifth habit is worth adding because the error is so common in coverage of this project. Wafer diameter is not a node. The Dholera fab is described as a 300 millimetre fab and as a 28 to 110 nanometre fab, and those two numbers describe unrelated things: the first is the size of the silicon disc that travels through the line, the second is the generation of the process printed onto it. Larger wafers lower the cost per chip because a single pass of a tool processes more area, which is why 300 millimetre is the volume standard while much mature capacity elsewhere still runs on 200 millimetre discs. A fab can run a mature process on large wafers, which is precisely the combination chosen here, and it is a cost decision rather than a technology claim. Confusing the two produces the recurring assertion that a 300 millimetre fab must be advanced, which does not follow.
For this record the practical consequence is narrow. A mature node fab is not a consolation prize and it is not a leading edge plant in disguise. It is a specific industrial proposition with a known product set, a well understood demand profile and a known set of risks, chief among them that its tools are new while its competitors' are paid off. The corporate side of that proposition is tracked at the Tata Electronics file and the technology transfer arrangement behind it at the Tata and PSMC partnership.