Guide

India's chip design industry: the layer that was already here

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

India has been designing chips for other people's fabs for decades, which is why the arrival of a domestic fab is a smaller change for designers than it sounds.

The one layer where India is not a beginner

Every discussion of Indian semiconductors starts with fabs, which inverts the actual history. Chip design work has been done in India for decades, first inside captive centres of global chipmakers and then across a services industry that grew large enough to be quoted in the government's own case for the manufacturing push. The figure that travels furthest is that India employs close to 20 percent of the world's semiconductor design workforce, stated in a Rajya Sabha reply by the Minister of State for Electronics and Information Technology on 13 March 2026 and repeated in mission material and ministerial speeches through 2026 REPORTED .

This record carries that number at reported tier for a specific reason. No public document sets out the denominator, the job categories counted, or the survey behind it. A figure that is quoted identically for years without a published count is an official estimate, not a measurement, and treating it as measured is how a plausible number becomes an unchallengeable one. What is verifiable is narrower and still substantial: India hosts a very large concentration of design employment inside global companies, and the Press Information Bureau's June 2026 document records more than 2,100 global capability centres across 3,728 units employing about 2.36 million professionals across all industries, of which semiconductors are one slice DURABLE .

What "design" actually covers

The word hides an industry with several distinct businesses inside it, and conflating them produces most of the bad analysis in this area.

• Design services. Engineering sold by the hour or by the project: register-transfer-level coding, verification, physical design, design for test, timing closure. The customer owns the chip. This is the largest Indian activity by headcount.
• Captive design centres. The same work done inside a global chip company's own Indian subsidiary. The output is the parent's product, and the Indian entity books cost, not chip revenue.
• Intellectual property cores. Reusable blocks licensed to others, a product business with software economics and a long qualification cycle.
• Fabless product companies. Firms that own a chip, sell it, carry the inventory risk and keep the margin. This is the layer India has least of, and the layer the Design Linked Incentive Scheme was written to grow.

All four depend on a foundry somewhere, and specifically on a process design kit, the electronic description of what a given fab can actually build. That dependency is the hinge between design and manufacturing, and it is explained properly in our design enablement page. A designer without access to a process design kit at the right node cannot start, whatever their skill.

Why design leadership never produced fabs

The obvious question is why a country with this much design employment took until 2024 to break ground on a commercial fab. The answer is that the two businesses have almost nothing in common financially. A design centre is an operating expense: people, tool licences, office space, and it can be started, scaled or closed within a year. A wafer fab is a capital project, with a ticket of Rs 91,526 crore in the Dholera case, a construction period measured in years, and utilities requirements that put it in the same conversation as a refinery. Design capability compounds with talent; fabrication capability compounds with process knowledge accumulated on a running line, which cannot be hired in.

The second reason is that Indian designers never needed a domestic fab. Global foundries sold capacity to anyone with a design and a purchase order, so the absence of a local plant was an inconvenience rather than a blocker. India's earlier fab attempts, in the rounds of the late 2000s and 2010s, failed for reasons that had little to do with design capability, and that history is set out in our semiconductor history guide. The 2021 programme changed the incentive structure rather than the engineering logic.

What the design scheme has actually produced

The Design Linked Incentive Scheme carries an outlay of Rs 1,000 crore and supports startups and smaller companies with research support and incentives of up to Rs 15 crore per company, per the Press Information Bureau backgrounder of 7 February 2026 DURABLE . Its published results are more specific than most Indian scheme reporting.

• 24 companies had received fiscal support and 105 applicants had received electronic design automation tool support as of March 2026, per the June 2026 document DURABLE .
• Startups had completed 16 tape-outs, with seven chips fabricated as of March 2026, including designs at nodes as advanced as 12nm.
• Supported startups had attracted nearly Rs 430 crore in venture capital as of January 2026, per the February 2026 backgrounder.
• The national design platform had recorded about 2.25 crore tool hours, with around 67,000 students and over 1,000 startup engineers using the tools.
• Academic users had taped out 122 designs with 56 chips fabricated at 180nm at the Semiconductor Laboratory in Mohali, and had filed 75 patents against 10 filed by startups.
• The stated next-phase target is at least 50 fabless semiconductor companies TARGET .

Seven fabricated chips from 16 tape-outs is a small number in absolute terms and a meaningful one for a scheme of this age, because a tape-out is the point at which a design stops being a document and starts costing mask money. The gap between 24 supported companies and a target of 50 fabless firms is the scheme's whole thesis: that capital plus tool access converts service engineers into product owners. Our fabless guide tracks who is actually shipping, and the startup guide handles the survival math.

The indigenous processor programme

Running alongside the incentive scheme is a public design effort aimed at processors rather than companies. The February 2026 backgrounder records the launch of DHRUV64, a 64-bit microprocessor developed by the Centre for Development of Advanced Computing under the Microprocessor Development Programme, positioned for 5G infrastructure, automotive electronics, industrial automation and connected devices DURABLE . It joins an existing portfolio of Indian processors including SHAKTI, AJIT, VIKRAM and THEJAS, developed under the Digital India RISC-V programme, which uses the open RISC-V instruction set to avoid architecture licence costs. Further system-on-chip variants named DHANUSH and DHANUSH plus are described as under development TARGET .

The honest read is that these are capability programmes rather than commercial products so far. A processor becomes an industry when volume customers design it into shipping systems, and no such volume record is public. What the programme does buy is a domestic skill base in architecture and system-on-chip integration, which is a different and deeper skill than verification services, and a set of designs that public buyers can specify without an export-control conversation.

The tools, and who owns them

A design industry runs on software that a small number of companies sell, and the economics of that software shape who can enter. Electronic design automation covers simulation, synthesis, place and route, timing and power analysis, physical verification and the checks that confirm a layout obeys a foundry's rules. Licence pricing is built for corporate buyers, which is why tool access rather than talent is the first wall a two-person design startup meets. That is the barrier the Indian programme attacked directly, by buying shared access rather than by asking startups to buy their own: about 2.25 crore tool hours had been recorded on the national design platform as of the February 2026 backgrounder, used by around 67,000 students and over 1,000 startup engineers DURABLE .

Tool access alone does not close the gap. Three further dependencies sit behind any chip. The first is the process design kit, supplied by whichever foundry will build the part, without which the tools have nothing to target. The second is third-party intellectual property: memory compilers, interface blocks, standard cell libraries and processor cores, most of which are licensed from outside India, and many of which are qualified for specific foundry processes rather than being freely portable between them. The third is mask cost, which is charged per tape-out and rises steeply with node advancement, and which is the reason a scheme measures its progress in tape-outs rather than in designs completed.

The open instruction-set route is the one structural response India has made to the second dependency. Building the public processor family on RISC-V removes an architecture licence and the negotiation that comes with it, which is why the same architecture appears repeatedly across the public designs. It does not remove the rest of the stack, and this record has seen no public claim that any Indian design flow is free of licensed third-party blocks.

Export controls touch the layer lightly at the mature end and heavily at the advanced end. Tools, cores and manufacturing services are all controlled items in the jurisdictions that supply them, but the controls that dominate news coverage are aimed at leading-edge logic and high-bandwidth memory, not at the 28 to 110nm range the domestic fab will run. An Indian design house working on power management, connectivity or industrial parts operates well inside the permitted band today. That is a comfortable position and a narrow one, and it is worth stating plainly rather than celebrating: the freedom exists because the work is not at the frontier.

The pipeline underneath all of it

The design industry's constraint is not tools, it is people who have taped out something real. The Chips to Startup programme, launched in 2022 with an outlay of Rs 250 crore over five years, targets 85,000 industry-ready professionals and has put shared design infrastructure in front of about one lakh individuals across 400 organisations, including 300 academic institutions and 95 startups, with more than 265 industry-led training programmes run, per the June 2026 document DURABLE . The ChipIN Centre at Mohali ran six shared wafer runs enabling 122 chip design submissions from 46 institutions, and participating institutions report more than 500 intellectual property cores, application-specific circuits and system-on-chip designs under development.

Shared wafer runs are the mechanism that matters most in that list. A student who has watched a design come back as silicon and fail in a measurable way has learned something no course delivers. Six runs across four years for a country this size is a thin cadence, and it is the number to watch as the domestic fab base grows. The education guide maps the degree programmes feeding this pipeline.

What a domestic fab actually changes for designers

Less than the rhetoric suggests, and more than the sceptics allow. The Dholera plant's stated node range is 28 to 110nm, its capacity is about 50,000 wafer starts per month on 300mm wafers, and commercial production is guided to mid-2028, with the opening node reported as mostly 90nm by Bloomberg on 17 July 2026 and TrendForce on 20 July 2026 against the 28nm start described in the Tata Sons chairman's FY25 letter REPORTED . Nothing in that range serves an artificial-intelligence accelerator or a modern application processor, so designers working at advanced nodes will keep buying capacity abroad.

What changes is access at the mature end. A domestic foundry running power management circuits, display drivers, microcontrollers and analog parts creates the possibility of local process design kits, shorter iteration loops, and multi-project wafer runs for small volumes, which is exactly what a young fabless company cannot buy easily from a large overseas foundry. Whether Dholera will offer shuttle runs to Indian design houses is not public, and this desk will not assume it. Today the only domestic option for small academic and startup runs is the 180nm line at Mohali. The mature node guide explains why that end of the market is bigger and more durable than its reputation.

What to watch

Four signals will tell you whether the design layer is converting into an industry rather than a workforce. The first is product ownership: an Indian fabless company shipping in volume with its own name on the part. The second is whether the Dholera fab publishes a design enablement offer, including any shuttle programme, when it approaches production. The third is the graduation rate under the design scheme, measured as supported companies reaching commercial revenue rather than tape-outs completed. The fourth is retention, because a design workforce is portable in a way a fab is not, and the same 20 percent claim can describe either a national asset or a global company's cost centre. This record will score all four on published evidence and will keep the official estimates labelled as estimates.