Guide

The India Semiconductor Mission, explained: schemes, money and the scoreboard

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

The mission is not a cheque book, it is an appraisal body whose decisions are taken one level above it, and its record is now long enough to score.

What the mission is, and what it is not

The India Semiconductor Mission is usually described as a subsidy scheme, which is the least useful way to read it. The mission is an executive body inside the Ministry of Electronics and Information Technology. It takes proposals from companies, appraises them against the terms of four separate schemes, and routes the ones it accepts upward for a decision it does not itself take. Every approved unit in the country carries a dated Union Cabinet decision rather than an administrative order from the mission, which is a precise indication of where the authority sits. How proposals are scored inside that appraisal is not published, so this record does not describe the process. What is public is the output: a list of Cabinet decisions with dates, companies, states and capital numbers attached.

The programme underneath the name is older than the name most people use. The Union Cabinet approved the Semicon India Programme in December 2021 with an incentive framework of Rs 76,000 crore, and that framework offers fiscal support of up to 50 percent for silicon fabs, compound semiconductor facilities, assembly and testing units and chip design, per the Press Information Bureau backgrounder titled India Semiconductor Mission 2.0, dated 7 February 2026 DURABLE . The mission is the delivery arm of that programme. When a minister says the mission approved a project, the accurate translation is that the mission appraised it and the Cabinet cleared it under one of the four schemes.

Two consequences follow, and both matter when reading announcements. An approval is an entitlement to a capped share of eligible project cost, not a transfer of cash, so the gap between an approval headline and money leaving the treasury can be long. And because the Cabinet is the deciding body, approvals arrive in clusters on Cabinet days rather than continuously, which makes the approval record look lumpier than the underlying pipeline probably is. Readers who track the programme by press-release frequency will mistake the calendar of Cabinet meetings for the pace of industrial policy.

The four schemes, one by one

The February 2026 backgrounder sets out the programme's instruments plainly, and they are worth separating because they buy very different things at very different prices.

• Semiconductor Fabs Scheme. Up to 50 percent fiscal support for wafer fabrication units, covering advanced and mature technology nodes. One project has been cleared under it: the Tata Electronics plant at Dholera, in technology partnership with Powerchip Semiconductor Manufacturing Corporation of Taiwan.
• Display Fabs Scheme. Up to 50 percent financial support for AMOLED and LCD display fabrication units. No AMOLED or LCD panel fab appears anywhere in the approval record, and the mission's own composition of its 12 projects, one semiconductor fab, two compound semiconductor fabs and nine packaging units, contains no display fab category at all. A display panel plant, a display driver chip plant and a Mini or Micro-LED module plant are three different industries; the second and third are in the record and the first is not.
• Compound Semiconductors, Silicon Photonics, Sensors, Discrete Fabs and ATMP or OSAT Scheme. Up to 50 percent capital assistance for compound semiconductor plants and for assembly, testing, marking and packaging units. This is the workhorse of the programme by project count.
• Design Linked Incentive Scheme. An outlay of Rs 1,000 crore, supporting chip design startups and micro, small and medium enterprises through research support and incentives of up to Rs 15 crore per company.

Notice the asymmetry. Three of the four schemes buy factories, and the fourth carries an outlay of Rs 1,000 crore against a framework of Rs 76,000 crore. That ratio is the programme's implicit theory: India already has design people and needed plants. Whether that theory holds is the argument the chip design industry guide takes up in detail.

What fifty percent fiscal support actually means

The headline instrument is a 50 percent share of eligible project cost committed by the Government of India. For the Dholera fab that commitment was formalised in a Fiscal Support Agreement signed on 5 March 2025 against a project cost of Rs 91,526 crore DURABLE . The distance between a Cabinet approval, dated 29 February 2024 in that case, and a signed agreement a year later is itself a data point about how long the paperwork layer of industrial policy takes.

Approval establishes eligibility and a ceiling. An agreement of this kind is normally where the disbursement architecture sits: what counts as eligible capital expenditure, against what milestones money is released, what documentation triggers each tranche, and what happens if a project stalls. The terms of the Dholera agreement are not public, so none of that should be described as known in this case. In capital-intensive manufacturing generally, support of this type reimburses against certified spend rather than paying in advance, which means the promoter funds first and claims after. That ordering is why an approval headline and a bank balance are different objects.

States stack a second layer on top of the central share. Under the Gujarat Semiconductor Policy 2022-27, announced on 27 July 2022 and the first state semiconductor policy in India, the state contributes 40 percent of the capital assistance approved by the Centre, alongside land, water and power subsidies aimed at the inputs a fab consumes most ruinously DURABLE . The mechanics of that stacking, and what it does to the effective public share of a project, are worked through in how fab incentives work in India. The short version: the central 50 percent is a ceiling on the central share, not on total public support.

The scoreboard as of 25 August 2026

The mission's approval record is now long enough to read as a portfolio rather than a set of announcements. As of December 2025, 10 projects worth Rs 1.60 lakh crore had been approved across six states, per the February 2026 backgrounder. The Union Cabinet added two more units, both in Gujarat, on 5 May 2026 with a cumulative investment of about Rs 3,936 crore and 2,230 skilled jobs projected, taking the total to 12 projects worth about Rs 1.64 lakh crore, per the Cabinet decision reported on 5 May 2026 and confirmed in the Press Information Bureau document India's Emerging Technology Ecosystem of 22 June 2026 DURABLE . That later document also gives the composition: one semiconductor fab, two compound semiconductor fabs and nine packaging units.

The list checks out against itself, which is worth doing before quoting it. The ten individually published project values sum to Rs 1,60,365 crore, matching the Rs 1.60 lakh crore the mission reports for December 2025, and the May 2026 pair carries the total to about Rs 1.64 lakh crore. Read the shape rather than the total. One project carries more than half the capital in the portfolio, and it is the hardest thing anyone in the programme is attempting. The rest is a back-end and compound-semiconductor base whose individual tickets run from Rs 27,120 crore down to Rs 117 crore. The packaging guide takes the nine back-end units apart individually, and the project count answer keeps the running tally with dates.

The outcome budget nobody reads

Approval totals are cumulative and therefore flattering. The document that shows what the programme expects to happen in a single year is the outcome budget, and for 2026-27 the Modified Programme for Development of Semiconductor and Display Manufacturing Ecosystem in India carries a total financial outlay of Rs 8,000 crore, per the February 2026 backgrounder. The projected targets under it are unusually specific: one fab supported, with Rs 4,000 crore of investment during the year and 1,500 persons employed; nine compound semiconductor and assembly, testing and packaging units supported, with Rs 11,000 crore of investment during the year and 3,000 persons employed; and 30 design companies supported under the Design Linked Incentive Scheme, developing 10 semiconductor intellectual property cores and employing 200 design personnel TARGET .

Those are the numbers to score the programme against, because they are the ones the programme wrote about itself for a defined period. A cumulative approval total of Rs 1.64 lakh crore cannot be checked against anything. Rs 11,000 crore of investment by supported units during 2026-27, and 3,000 jobs at those units, can be. This desk treats the outcome budget as the scoreboard and the approval list as the roster.

The design and talent limbs

The programme's fourth scheme and its training programmes are the least covered part of the mission and the part with the most published detail. Under the Design Linked Incentive Scheme, 24 companies had received fiscal support and 105 applicants had received electronic design automation tool support as of March 2026, with seven chips fabricated from 16 tape-outs including designs at 12nm, per the June 2026 document. The February 2026 backgrounder adds that startups under the scheme had attracted nearly Rs 430 crore in venture capital funding as of January 2026, that about 2.25 crore tool hours had been recorded on the national design platform, and that academic users had taped out 122 designs with 56 chips fabricated at 180nm at the Semiconductor Laboratory in Mohali REPORTED .

The talent side runs on separate money. The Chips to Startup programme was launched by the Ministry of Electronics and Information Technology in 2022 with an outlay of Rs 250 crore over five years and a stated aim of developing 85,000 industry-ready professionals. Its published results as of June 2026 include shared design infrastructure reaching about one lakh individuals across 400 organisations, of which 300 are academic institutions and 95 are startups, and six shared wafer runs at the ChipIN Centre at Mohali enabling 122 chip design submissions from 46 institutions. Separately, a training lab at NIELIT Calicut targets one lakh engineers with more than 62,000 trained, and a partnership with Lam Research aims at 60,000 trained professionals over ten years. The programme audit on this desk tests those figures against what a fab floor actually needs.

ISM 2.0, and the two outlays people confuse

The second phase was announced in the Union Budget 2026-27 and is aimed at semiconductor equipment and materials manufacturing, full-stack Indian semiconductor intellectual property, resilient supply chains, research, training and advanced manufacturing. The February and June 2026 documents both describe an initial provision of Rs 1,000 crore for FY 2026-27 DURABLE . The mission's own website, read on 25 August 2026, presents Semicon 2.0 under six heads, chip design, machines and materials, more fabs, further strengthening of the assembly and test industry, research and development, and talent development, and states that the Union Cabinet has approved that phase with a fiscal outlay of Rs 1,27,500 crore DURABLE .

Those two figures are not the same kind of object, and the difference is the point. Rs 1,000 crore is a provision for a single financial year. Rs 1,27,500 crore is presented as a Cabinet-approved fiscal outlay for the phase as a whole, on a page that carries no date for that approval, and the February 2026 backgrounder that describes ISM 2.0 at length does not mention the larger figure anywhere. This record prints both with their sources, treats the larger number as a phase outlay rather than an appropriation, and will date it when a dated primary release supports it. Anyone quoting Rs 1,27,500 crore as money spent, or as money available during 2026-27, is conflating a phase outlay with a budget line. The same discipline applies to the pipeline talk that surrounds Dholera, where reported pipeline figures are routinely reprinted as committed capital; our capital ledger keeps the two columns apart.

How this record will score the mission

Announcements will remain plentiful, so the scoring has to run on delivery. Four tests carry most of the weight. The first is Dholera, where commercial production is guided to mid-2028 by the Minister for Electronics and Information Technology, speaking on 17 July 2026, and where no first-silicon date is supported by any source this record accepts TARGET . Civil progress at the site was about 50 percent as of mid-2026 with cleanroom fit-out under way, and the plant's opening node is reported by Bloomberg on 17 July 2026 and TrendForce on 20 July 2026 as mostly 90nm against the 28nm start described in the Tata Sons chairman's FY25 letter, a contradiction neither party has resolved REPORTED .

The second test is whether the nine packaging units convert approvals into qualified, invoiced output for customers who had a choice. The third is disbursement: the programme's credibility rests on money actually flowing against certified spend, and none of the fiscal support agreements are public. The fourth is the second phase, which will only be real when an Indian company ships a qualified production tool or material into a fab that could have imported one. Until then, ISM 2.0 is a budget line and a set of intentions, and this desk will report it as such. The budget answer keeps the money figures current as the documents change.