Guide

Fabless companies in India: the thin layer where somebody actually owns the chip

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

India has an enormous chip design workforce and a very small number of companies that own a chip and sell it. Those are different industries, and the difference is the whole story.

What fabless means, and why the word is used loosely here

A fabless company owns a chip. It defines the product, designs it, pays for the mask set, contracts a foundry to manufacture wafers, arranges assembly and test, holds the inventory, sells the part under its own name and keeps whatever margin survives. It carries the risk that the product does not sell, and it collects the reward if it does. That is a fundamentally different business from selling engineering hours, and in India the two are constantly conflated because both employ the same kind of engineer doing similar-looking work.

The distinction is not academic. A design services firm books revenue per engineer per month and can be profitable from its first project. A fabless product company spends money for two or three years before a single part ships, then faces inventory, distribution, customer support and obsolescence management for a decade. One is a labour business with predictable cash flow. The other is a venture business with a long negative curve and a chance of a large annuity at the end. India has built a very large amount of the first and a small amount of the second, and this page counts the second.

The wider design economy, including captive centres and the services industry that dominates it by headcount, is covered in our chip design guide. This page picks up where that one leaves off.

The rule this register runs on

Lists of Indian fabless companies circulate freely and most of them are unreliable, mixing design services firms, captive subsidiaries of foreign chipmakers, systems companies with an internal chip team, and genuine product companies into a single tally that flatters everyone. A company appears on this page only when a government release or a dated public announcement establishes both that the company exists as an Indian design-product firm and what it is building. Where the only available detail is a company's own description of its work, this record says so and tiers it accordingly. Where a name circulates in listicles without a traceable primary record, it is omitted rather than hedged, because an omission is honest and a hedged entry is a claim.

One consequence of that rule should be stated plainly at the top. The verifiable Indian fabless layer is small, young and mostly pre-revenue at scale. Anyone who tells you otherwise is either counting services firms as product companies or quoting a market research total that nobody can audit.

What the design incentive scheme has actually produced

The Design Linked Incentive Scheme is the instrument the government built specifically to convert design capability into product ownership. Its outlay is Rs 1,000 crore, with research support and incentives of up to Rs 15 crore per company, per the Press Information Bureau backgrounder of 7 February 2026 DURABLE. Its published results are unusually specific for an Indian scheme, which makes it the only defensible spine for a page like this one.

• Twenty-four companies had received fiscal support and 105 applicants had received electronic design automation tool support as of March 2026, per the government's June 2026 semiconductor document. An earlier release recorded 23 sanctioned chip-design projects, so the count is moving.
• Supported startups had completed 16 chip design tape-outs, with seven chips fabricated as of March 2026, including designs at nodes as advanced as 12nm DURABLE. Some government statements of the same period carried six fabricated chips rather than seven, which is consistent with a count that was changing during the reporting window.
• Supported startups had attracted nearly Rs 430 crore in venture capital as of January 2026, per the February 2026 backgrounder, and had filed ten patents against 75 filed by academic users of the national design platform.
• The stated next-phase goal is at least 50 fabless semiconductor companies TARGET.

Trade coverage during 2026 has carried larger figures, including a cumulative count of 35 tape-outs and more than 100 million dollars raised across the supported cohort REPORTED. This record keeps the March 2026 government-documented numbers as its baseline until a dated primary release supersedes them, and notes the higher figures as reported rather than adopting them. The difference matters because tape-out counts are the most quoted and least standardised metric in this field: a test chip, a shuttle run and a production-intent design all count as a tape-out to whoever is counting.

Read the baseline honestly and it says something specific. Sixteen tape-outs and seven fabricated chips is small in absolute terms and meaningful for a scheme of this age, because a tape-out is the moment a design stops being a document and starts costing mask money. The gap between 24 supported firms and a target of 50 is the scheme's entire thesis: that capital plus tool access converts service engineers into product owners.

The companies named on the public record

On 27 January 2026 the electronics and information technology minister, Ashwini Vaishnaw, held an interaction in New Delhi with chip design companies approved under the scheme, recorded by the Press Information Bureau, and the accompanying descriptions of the participating firms are the clearest public identification of who these companies are and what they are building DURABLE. The product descriptions below come from the government's account of that interaction and from the companies' own published descriptions of their work, which makes them company-stated claims rather than independently measured outcomes REPORTED.

Several patterns are visible in that table and worth naming. The chosen segments are narrow and defensible rather than broad: edge vision, motor control, satellite beamforming, radar sensing, broadband networking. None of these companies is attacking a general-purpose market against an entrenched global incumbent, which is the correct strategy for a small product company and also the reason the individual revenue opportunities are modest. Several of the designs are built on Indian processor cores rather than licensed foreign architectures, which reduces licence cost and export-control exposure at the price of a smaller software ecosystem. And the recurring phrase across announcements is first-pass silicon success, which is a genuine engineering achievement and not the same thing as a shipping product with volume customers.

The public processor programmes underneath

Two of the companies above build on processor cores that came out of public programmes, which is a structural feature of the Indian fabless layer rather than a coincidence. The Shakti family from IIT Madras and the VEGA family from the Centre for Development of Advanced Computing exist because Indian institutions built open-instruction-set processors, and their availability lowers the entry cost for a startup that would otherwise pay architecture licence fees before writing a line of code.

The February 2026 backgrounder also records the launch of DHRUV64, a 64-bit microprocessor developed by the Centre for Development of Advanced Computing under the Microprocessor Development Programme, positioned for telecom infrastructure, automotive electronics, industrial automation and connected devices, alongside an existing portfolio that includes SHAKTI, AJIT, VIKRAM and THEJAS under the Digital India RISC-V programme. The honest read is that these are capability programmes. A processor becomes an industry when volume customers design it into shipping systems, and no such volume record is public. What they do provide is a domestic architecture base that fabless firms can build on, which is precisely how Vervesemi's motor controller and Aheesa's broadband device came to exist.

Why fabless is harder than services, in cash terms

The reason India's fabless layer is thin is not talent. It is the shape of the cash curve, and it is worth setting out concretely because it explains every policy instrument aimed at this problem.

• Tool licences come first. Electronic design automation software is priced for corporate buyers, and a two-person startup meets that wall before it meets any technical problem. Shared tool access is the reason the national design platform exists.
• Mask sets are a hard cash event. At mature nodes a mask set is a manageable but real cost, and at advanced nodes it is a company-defining one. A design error discovered after tape-out is paid for twice.
• Foundry access requires scale or a friend. Foundries allocate capacity and engineering attention by volume, and a first-time customer with modest wafer numbers is not a priority. Shuttle programmes and multi-project wafers exist to bridge this and do not solve it at production volume.
• Qualification is unpaid work. Between working silicon and a purchase order sit months of characterisation, reliability testing and customer evaluation, funded entirely by the designer.
• Inventory and support last a decade. Once a part is designed into a customer's product, the fabless company owes availability, failure analysis and change control for as long as the product ships.

Against that curve, a services contract that pays monthly from month one is not a failure of ambition. It is a rational response to capital scarcity, and it is why the government instrument targets exactly the segment of the curve where private capital has been least willing to sit. Our startups guide handles the survival mathematics of this in more detail.

What a domestic fab actually changes for a fabless company

The intuitive answer is that a domestic fab gives Indian designers somewhere to make their chips, and the intuitive answer is only partly right. What matters is not geography but access, terms and the process design kit.

The Tata Semiconductor Manufacturing plant at Dholera is designed for up to 50,000 wafer starts per month on 300mm wafers in a 28 to 110nm band, at Rs 91,000 crore with central support covering 50 percent of eligible cost DURABLE, with commercial production guided to mid-2028 TARGET. For a domestic fabless firm the significant consequences are these. A design kit for a mature process becomes available in the same time zone, with support engineers reachable in a working day, which shortens the debugging cycle that kills small teams. Small customers may find allocation easier to obtain from a plant that needs to fill a ramping line than from an established foundry with a queue. And payment in rupees against a domestic supplier removes a currency and customs layer from a small company's working capital.

What it does not change is equally important. A fab at 28 to 110nm does not serve a designer who needs an advanced node, and several of the more ambitious Indian designs have taped out at 12nm, which is outside this plant's range. It does not remove the qualification burden, the tool licence cost or the inventory risk. And there is an existing domestic option that is often forgotten: the Semiconductor Laboratory at Mohali has fabricated academic designs at 180nm, with 122 designs taped out and 56 chips fabricated by academic users per the government record, which is a real if narrow capability described in our SCL guide.

The gap this page exists to name

India employs an estimated share close to 20 percent of the world's semiconductor design workforce, a figure repeated in official statements including a Rajya Sabha reply of 13 March 2026 REPORTED. No published headcount underlies it, so this record carries it as an official estimate rather than a measurement. Even taken at face value, it describes engineering employment, not chip ownership, and the two have never been the same thing.

The honest position is that India's semiconductor design layer is dominated by services and captive engineering rather than by product ownership, that the fabless product layer consists of a small number of young companies most of which have working silicon rather than volume revenue, and that this record has identified no published revenue figures for any Indian fabless product company that would establish commercial scale. That is not a criticism of the companies named above, several of which have done difficult engineering on modest capital. It is a description of an industry at an early stage, and describing it accurately is more useful to a reader than inflating it.

The second phase of the national programme is written partly against this gap. The Union Cabinet approved Semicon 2.0 on 15 July 2026 with a total budget outlay of Rs 1,27,500 crore, per Press Information Bureau release 2284784 of that date, structured across pillars that include chip design alongside machines and materials, more fabs, assembly and test, research and talent DURABLE. Whether an outlay converts into product companies is a question the scoreboard below will answer over the next several years, not an argument to be settled now.

What is not public, and what to watch

Four things would settle most of the open questions and none of them are published: individual company revenues, which would show whether any Indian fabless firm has reached commercial scale; the unit volumes behind the announced first-pass silicon successes, which separate a demonstration from a product; the identity of the customers designing these parts into their own systems; and a company-by-company breakdown of the scheme's disbursements against milestones, which would show how much of the Rs 1,000 crore outlay has actually moved.

• A shipped part in a named product. This remains the clearest possible evidence and it is still rare, because an Indian chip inside an Indian-manufactured device sold at volume changes the argument entirely.
• Movement toward the 50-company goal. Watch the count of supported firms, and more importantly the count still trading three years after the support arrives.
• A significant private funding round. Venture capital that is not following the government in is the market's own verdict on this layer.
• An Indian fabless firm as a Dholera customer. This would be the single most meaningful link between the design layer and the manufacturing layer, and it would validate both at once. Our product answer tracks the fab side of that question.
• Consolidation. Acquisitions of Indian product companies, by anyone, would tell you the assets are considered valuable and would also test whether India can keep product ownership rather than exporting it.