Guide

Chips to Start-up: auditing India's chip-design talent programme on its own numbers

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

C2S is the rare Indian programme that publishes enough detail to be graded properly, so this page grades it on the figures the government itself printed rather than on the adjectives around them.

What C2S is, precisely

Chips to Start-up is a capacity-building programme run by the Ministry of Electronics and Information Technology, launched in 2022 with a total outlay of Rs 250 crore over five years, per the Press Information Bureau backgrounder on the programme dated 18 January 2026 DURABLE. Its purpose is narrower than the coverage suggests. C2S does not train fab operators, and it does not build clean rooms. It gives academic institutions access to industrial chip-design software, funds design projects, and routes the resulting designs to a real fabrication line so that students hold a chip they designed.

The headline target is 85,000 industry-ready professionals across undergraduate, postgraduate and doctoral levels. The same backgrounder breaks that number down, which is the detail that makes the programme auditable: 7,000 M.Tech graduates specialising in VLSI or embedded systems, 8,800 M.Tech graduates from computer, communication or electronic systems programmes with focused VLSI exposure, and 69,000 B.Tech students trained through VLSI-oriented coursework. Beyond manpower, the programme states targets of 25 start-ups incubated, ten technology transfers, one lakh students trained, 50 patents and at least 2,000 focused research publications.

Read the breakdown once more and the shape of the ambition becomes clear. Roughly four fifths of the 85,000 is undergraduate coursework exposure, not specialist postgraduate training. That is not a criticism, because broad exposure is how any country builds a base. It is a correction to the way the figure is usually deployed, which implies 85,000 chip designers rather than 85,000 people who have touched chip design.

The machinery: ChipIN, SCL Mohali and a shared wafer

The programme's engine room is the ChipIN Centre at C-DAC Bengaluru, which the January 2026 backgrounder describes as one of India's largest facilities for shared semiconductor design infrastructure. Its mechanism is worth understanding because it is genuinely clever and rarely explained.

Students at participating institutions design chips using electronic design automation tools provided centrally. The ChipIN Centre collects those designs, verifies that each meets fabrication requirements, works with students through revisions, and then groups approved designs together every three months onto a single shared wafer. That wafer goes to the Semi-Conductor Laboratory at Mohali, which fabricates at 180 nanometres, packages the results and delivers the chips back to the students. The economics of this are the point: a dedicated wafer run for a single student design would be unaffordable, while a shared run divides the mask set and wafer cost across dozens of designs, which is the only arrangement under which student silicon is affordable at all. India's existing line at Mohali, which does the fabricating, has its own file at SCL Mohali.

The scoreboard, as published

The 18 January 2026 backgrounder gives the fullest published account of outcomes to date. Around one lakh individuals from about 400 organisations, comprising 300 academic institutions and 95 start-ups, have used shared national design infrastructure, generating more than 175 lakh hours of tool usage. The ChipIN Centre organised six shared wafer runs at SCL Mohali, enabling 122 chip design submissions from 46 institutions. Of those, 56 student-designed chips were fabricated, packaged and delivered. More than 265 industry-led training sessions were conducted, participating institutions have filed over 75 patents, and institutions are developing more than 500 intellectual property cores, application-specific integrated circuits and system-on-chip designs. The centre has also addressed 4,855 technical support requests DURABLE.

The India Semiconductor Mission 2.0 backgrounder of 7 February 2026 adds the design-incentive side and one important cross-check. Under the Design Linked Incentive scheme as of January 2026, 24 semiconductor design start-ups were supported, those start-ups had attracted nearly Rs 430 crore in venture capital funding, the national design platform had recorded approximately 2.25 crore tool hours, and around 67,000 students plus over 1,000 start-up engineers were actively using the tools. In academia, 122 designs had been taped out with 56 chips fabricated at 180 nanometres at Mohali. Start-ups completed 16 tape-outs, producing six chips at advanced foundry nodes including 12 nanometres, and academic institutions had filed 75 patents against ten from start-ups DURABLE.

Where the government's own numbers disagree

Three discrepancies appear across official documents published within five months of each other, and a record that prints one figure while ignoring the others is not keeping a record.

• Institution counts. The January 2026 backgrounder gives about 400 organisations, of which 300 to 305 are academic institutions under C2S and 95 are start-ups under the design incentive scheme. The February 2026 backgrounder says the programme enables access to design tools across 397 universities and start-ups. A table inside the January document separately describes 100-plus participating academic institutions as beneficiaries of project funds, tools and training, with 200-plus other organisations receiving tools and training only. Those are not contradictions so much as three different definitions of participation, and the funded tier is roughly a third of the headline count.
• Chips fabricated. The February 2026 document records six chips fabricated by start-ups from 16 tape-outs. The backgrounder of 22 June 2026 records seven chips fabricated from the same 16 tape-outs, alongside 24 companies receiving fiscal support and 105 applicants receiving design-tool support as of March 2026 DURABLE. The likeliest explanation is simply that one more chip came back between January and March, which is what progress looks like at this scale.
• Trained versus enrolled. Over one lakh individuals have enrolled in chip design training and approximately 67,000 had been trained by January 2026, per the C2S backgrounder. The gap between those two numbers is the ordinary attrition of any large training programme, and quoting the enrolment figure as though it were the training figure is the most common error in secondary coverage.

None of these is scandalous. All of them matter if you intend to cite a number, and naming them is cheaper than being corrected later. This desk's standards require the discrepancy to be printed alongside the figure rather than resolved silently.

The programmes C2S is constantly confused with

Four adjacent initiatives get folded into C2S in coverage, and each does a different job.

• The Design Linked Incentive scheme, launched in 2021, supports design start-ups and micro, small and medium enterprises with fiscal incentives and design infrastructure. It is a company programme, not an education programme, and its beneficiaries are counted separately. The commercial layer it feeds is mapped in our guide to the chip design industry in India.
• The SMART Lab at NIELIT Calicut, which supports large-scale training in semiconductor technologies, targets one lakh engineers nationally with more than 62,000 already trained, per the 7 February 2026 backgrounder DURABLE. This is a separate pipeline from C2S and its numbers should never be added to the C2S total.
• The training partnership with Lam Research, a large-scale programme in nanofabrication and process engineering aimed at assembly, test and advanced packaging skills, which states an aim of 60,000 trained professionals over the next ten years TARGET. This is the one on the list that points at manufacturing rather than design.
• AICTE programmes and FutureSkills PRIME, which embed VLSI content into curricula and deliver online upskilling respectively.

The gap C2S does not close

Here is the honest audit finding, and it is not a criticism of the programme so much as a warning against expecting it to do a job it never claimed. C2S produces chip designers. A wafer fab needs process engineers, equipment engineers, facilities specialists and a large tier of shift technicians who keep tools running to specification, and it needs them in the year the tools arrive. Designing at 180 nanometres through a shared wafer run teaches design flow, verification discipline and the reality of a fabrication schedule. It does not teach a technician to recover an implanter or hold a deposition chamber inside its process window.

The fab-side pipeline is a separate build, running through the Lam Research partnership, through the training rotations that technology partnerships typically involve, and through employers hiring from adjacent process industries. The mechanics of how a fab staffs up are covered at the fab talent ramp, and the job-seeker's view of the whole market sits at semiconductor careers in India. This page is the programme audit; those are the other two halves of the same subject, and the education system itself is mapped at semiconductor education in India.

There is a second gap worth naming. The 56 fabricated academic chips are an excellent teaching outcome and a modest industrial one, because 180 nanometres at Mohali is a long way from a commercial product at a modern node. The start-up track, with six to seven chips at advanced foundry nodes including 12 nanometres, is the part of the record that speaks to commercial capability, and it is currently roughly an order of magnitude smaller in count.

What Rs 250 crore buys, in proportion

Put the programme's budget beside the manufacturing money and the picture sharpens. C2S carries Rs 250 crore over five years. The Semicon India Programme's first-phase incentive framework is Rs 76,000 crore, and on 15 July 2026 the Union Cabinet approved Semicon 2.0 with a total budget outlay of Rs 1,27,500 crore, per Press Information Bureau release 2284784 of that date DURABLE. On those published figures the talent programme is roughly a three-hundredth of the first framework and roughly a five-hundredth of the second, which is arithmetic on three government numbers rather than a judgement about any of them. The second-phase approval is an outlay rather than money spent, so what it eventually pays for is still a matter of scheme guidelines that have not been published; design is named as the first of its six pillars, which is the reason to expect the design side of this ledger to move, and the reason this record will read those guidelines rather than assume a figure for training now.

Whether that ratio is wrong depends on what you think the money buys. Design training is cheap per head because the expensive inputs, meaning software licences and fabrication slots, can be shared across hundreds of users, and the January 2026 backgrounder's figures show exactly that sharing at work: about one lakh users, more than 175 lakh hours of tool time, six shared wafer runs. Manufacturing money buys a building and machines that nobody else can use. The two are not competing for the same job, and the honest observation is not that C2S is underfunded but that a programme this small cannot be expected to close a workforce gap the size of a national industry's.

What the design ecosystem has produced beyond training

Training numbers are inputs. The outputs worth watching sit slightly to the side of C2S, in the indigenous processor work that the same design ecosystem feeds. The 7 February 2026 backgrounder records the launch of DHRUV64, a fully indigenous 64-bit microprocessor developed by C-DAC under the Microprocessor Development Programme, positioned for use in 5G infrastructure, automotive electronics, industrial automation and connected devices DURABLE. It joins an existing portfolio of Indian processors including SHAKTI, AJIT, VIKRAM and THEJAS, developed under the Digital India RISC-V programme, with DHANUSH system-on-chip variants in development.

Those are research and strategic-capability outputs rather than commercial volume products, and this record does not claim more for them than that. Their relevance to a talent audit is specific: a design programme that produces only graduates is a training scheme, while one that produces working silicon and the teams that made it is the beginning of an industry. On the published record, India has some of both, with the volume heavily on the training side.

What would prove the programme worked

Not enrolment, which is already above one lakh. Not tool hours, which are above 175 lakh. Four things, in rough order of difficulty. First, employment conversion: a published figure for how many C2S-trained graduates entered semiconductor roles, which no document this desk has seen yet provides. Second, product survival: designs from the programme that reach a commercial customer rather than a demonstration board. Third, start-up formation against the stated target of 25 incubations and ten technology transfers, with the Rs 430 crore of venture funding under the design incentive scheme as the early market signal. Fourth, the arrival of a domestic hiring pull large enough that the training pipeline is chasing demand rather than creating supply in advance of it.

The last of those depends on plants, not on programmes. A design graduate needs somewhere to design for, and the fabless layer that would employ them is examined at fabless companies in India. On the published record, C2S has done the part a ministry can do: put tools, wafer runs and training in front of a hundred thousand people for Rs 250 crore, which is a small sum for that reach. Whether it produced an industry is a question that only the hiring numbers of 2028 and beyond can answer, and this desk will score it then rather than now.