The answer desk

What is an OSAT?

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

An OSAT is an outsourced semiconductor assembly and test company: a business that takes finished wafers from a fab, cuts them into individual chips, mounts and connects them, encapsulates them, tests them and ships them. Indian policy documents usually call the same work ATMP, for assembly, testing, marking and packaging. The distinction is business model rather than physics, since an OSAT sells that service to any customer while a captive plant serves only its owner. India started here because back-end plants cost far less than a wafer fab and reach revenue years sooner.

The definition, without the acronym soup

An OSAT is an outsourced semiconductor assembly and test provider. It is a factory that buys nothing you would recognise as a chip and sells everything you would: wafers arrive from a fab as discs of patterned silicon, and finished packaged devices leave in trays and on reels, tested, marked and ready to be soldered onto a circuit board. The company does not design the chip and does not fabricate the transistors. It performs the industrial steps between a working wafer and a sellable part.

Indian policy documents use a second term alongside it, and the pair causes more confusion than anything else in this subject. ATMP stands for assembly, testing, marking and packaging, and it describes the scope of physical work. OSAT describes the business model, meaning that the work is sold to external customers rather than performed on the owner's own products. The India Semiconductor Mission's own project pages use both labels, applying OSAT to some approved units and ATMP to others. The useful consequence is that a plant can perform ATMP without being an OSAT, and that difference decides whether an ecosystem forms around it, which is the part most coverage skips.

The vocabulary map that ends most of the confusion

• Fab. A wafer fabrication plant. It builds transistors and interconnect into silicon wafers. This is the front end, and it is the most capital-intensive step in the chain.
• Foundry. A fab that manufactures other companies' designs as a service. Every foundry is a fab; not every fab is a foundry, because some fabs make only their owner's products.
• Fabless. A company that designs and sells chips and owns no fab, buying wafers from a foundry and packaging from an OSAT.
• IDM. An integrated device manufacturer, which designs, fabricates and often packages its own products in its own plants.
• OSAT or ATMP. The back end: probe, thinning, dicing, die attach, interconnect, encapsulation, marking and final test.

Placed on a capital ladder, the ordering is stable across the industry: a leading-edge fab sits at the top, a mature-node fab well below it, and a conventional assembly and test plant lower again by a wide margin. The Dholera fab was approved at Rs 91,000 crore DURABLE. India's approved back-end plants were sanctioned at figures measured in thousands of crore, and the four units cleared on 12 August 2025 for Odisha, Punjab and Andhra Pradesh carried a cumulative investment of about Rs 4,600 crore between them DURABLE. That ratio, rather than any policy preference, is why the back end came first. Our three-letter map on the fab desk takes the taxonomy further.

What actually happens inside an OSAT

The sequence is worth knowing properly, because it explains both the cost structure and the skills a country acquires by building one.

Wafers arrive and go first to probe, also called wafer sort, where each die is tested electrically while still attached to the wafer. Probe cards with fine needles or bumps contact the pads, patterns are applied, and the results are recorded as a map of which dies pass. This matters commercially because packaging a bad die wastes the cost of the package and the labour, and the industry's term for the resulting quality question, known good die, becomes critical the moment more than one die goes into a single package.

The wafer is then thinned by grinding its back surface, since a full-thickness wafer is far thicker than most packages allow, and diced into individual chips with a saw blade or a laser. Good dies are picked and attached to a substrate or a metal leadframe with adhesive or solder. Electrical connection follows by one of two families of method: wire bonding, where fine gold, copper or aluminium wire is welded from a pad on the die to a lead, or flip chip, where the die is turned face down onto an array of solder bumps. The assembly is then encapsulated, usually in an epoxy moulding compound, and marked with its part identification.

Final test closes the process. Parts are exercised on automated test equipment, frequently across a temperature range, and sorted into bins by performance grade. Test is not a formality: test time is expensive, test equipment is capital-intensive, and the cost of test as a share of the finished part rises steeply as devices become more complex. Our back end explainer walks the same sequence from the engineering side.

Why the back end is the rational first rung

Four reasons recur wherever a country has entered this industry from a standing start. Capital intensity is an order of magnitude lower, so a first project is financeable without a national programme behind every rupee. Build time is shorter, typically two to three years to revenue rather than five to seven for a greenfield fab. Utility demands, while serious, are far below fab specification, since assembly does not need ultrapure water at fab volumes or the same class of vibration control. And the workforce profile suits an industrialising economy: precision assembly, equipment maintenance and test engineering are learnable at scale, where front-end process integration takes a decade to build.

The honest ceiling belongs in the same paragraph. Value captured per wafer is far lower in the back end than in the front end, conventional packaging is competitive and price-sensitive, and a country whose entire semiconductor position is assembly remains dependent on imported wafers. That is exactly why the sequencing argument matters: back end first, front end next, which is the shape of what Gujarat is now attempting with Sanand operating and Dholera building.

India's approved back-end plants, with dates

The register below carries what the government has approved and what has since been recorded as operating. Coverage through 2026 puts India's approved semiconductor portfolio at about 12 projects and roughly Rs 1.64 lakh crore of stated investment; the India Semiconductor Mission's own project pages, checked on 25 August 2026, list the projects individually without printing a single cumulative total, so this desk treats that total as an aggregation of dated Cabinet decisions rather than as a published figure REPORTED. National totals belong to the national programme and are never attributable to any one site.

The sourcing behind each row deserves stating. The Union Cabinet approved three units on 29 February 2024 with a cumulative investment of Rs 1.26 lakh crore: the Tata and Powerchip fab at Dholera at Rs 91,000 crore, the Tata Semiconductor Assembly and Test plant in Morigaon, Assam, reported at Rs 27,000 crore, and an assembly and test unit at Sanand DURABLE. Kaynes Semicon's Sanand unit was cleared in September 2024 at an investment of about Rs 3,300 crore, per the government announcements of 2 September 2024 DURABLE. The four units of 12 August 2025 were announced by the Press Information Bureau with a cumulative investment of about Rs 4,600 crore and a stated employment figure of 2,034 skilled professionals, comprising SiCSem and 3D Glass Solutions in Odisha, Continental Device India in Punjab and ASIP Technologies in Andhra Pradesh DURABLE. Two further units were cleared in May 2026 with a cumulative investment stated at more than Rs 3,900 crore, one of them Suchi Semicon's OSAT at Surat and the other Crystal Matrix's compound semiconductor and ATMP facility at Dholera DURABLE. Operating status for Micron, Kaynes, CG Semi and the Odisha and Uttar Pradesh projects is taken from the India Semiconductor Mission's own project pages as checked on 25 August 2026 DURABLE. Two notes on that register are owed to the reader: the mission's timeline records further CG Semi milestones during 2025 before the July 2026 inauguration, and it lists the Odisha glass and three-dimensional packaging project under a different corporate name from the one in the approval release, so this desk carries the approval name and the recorded milestone rather than asserting that the two entities are identical.

Two projects sit outside the table on purpose. SiCSem's Odisha plant, approved on 12 August 2025 in collaboration with Clas-SiC Wafer Fab of the United Kingdom, includes a silicon carbide compound fab as well as packaging, which makes it a front-end project with a back end attached rather than an OSAT. The HCL and Foxconn joint venture at Jewar in Uttar Pradesh, approved in May 2025 and recorded as breaking ground in February 2026, is a display driver chip unit, and whether it is filed as a fab or as a packaging project depends on which part of its scope you weight DURABLE. This record prefers naming the ambiguity to resolving it silently.

Captive against merchant, the distinction that decides everything

Two of India's most visible back-end plants are not OSATs in the strict sense, and the difference determines whether an ecosystem forms around them. Micron's Sanand plant packages Micron's own memory. Tata's Assam plant is being built by a group that also owns the Dholera fab. Both perform ATMP work. Neither, on the public record, sells that capacity to any customer who walks in.

A merchant OSAT changes the arithmetic for everyone around it, because a fabless design house anywhere in the country can send wafers to it, and because component suppliers, substrate makers and equipment service firms can build businesses against many customers rather than one. A captive plant creates jobs, skills and import substitution, and it does not create that pull. Kaynes Semicon, CG Semi and Suchi Semicon are the projects to watch on this axis, because a home-grown merchant packaging house winning external customers would be genuinely new for India.

Where conventional packaging stops and advanced packaging begins

Packaging used to be treated as commodity work performed after the interesting part. That has changed as transistor scaling has become slower and more expensive, and performance is increasingly extracted from how dies are combined: flip chip attachment, fan-out packaging where connections are redistributed beyond the die's own footprint, and 2.5D and 3D constructions where multiple dies sit on a shared interposer or stack vertically. Chiplet designs, which split a large chip into smaller pieces assembled into one module, made packaging a design decision rather than a finishing step.

India's approved base is mostly conventional, and saying so is not a criticism. Wire bond and flip chip assembly at volume is a real industry with real customers. Two approved projects reach towards the newer end: 3D Glass Solutions in Odisha for glass substrates and three-dimensional packaging, and ASIP Technologies in Andhra Pradesh for advanced system in package work, both approved on 12 August 2025. Our advanced packaging page explains the technologies themselves, and our packaging industry guide reads the sector as a whole.

Globally, the independent packaging industry is concentrated in Taiwan, China, South Korea, Malaysia and the United States, with ASE of Taiwan, Amkor of the United States and JCET of China among the best-known providers. India's entrants are competing for work in a mature service industry with established qualification relationships, which is a commercial challenge rather than a technical one.

How the back end connects to Dholera's front end

The obvious assumption is that wafers from the Dholera fab will be packaged at Sanand, roughly 100 kilometres away, completing a domestic chain. The public record does not support it. No published arrangement exists under which Dholera's wafers would be packaged at Sanand REPORTED, and there is a straightforward reason: Micron's plant handles Micron's memory, while Dholera will produce logic and analog parts at 28 to 110nm for customers who choose their own packaging partners. Wafers travel globally and cheaply relative to their value, so proximity is a convenience rather than a constraint. Our Dholera or Sanand answer exists because coverage confuses the two constantly.

What co-location genuinely creates is the option of an integrated chain, not the certainty of one, along with a shared supplier base, a shared labour market for test and equipment engineers, and a state administration that has now done both halves of the industry. Our Gujarat map holds the geography.

What to watch next

Four signals would tell you whether India's back-end wave is compounding or merely accumulating. Named external customers at an Indian merchant OSAT, which is the difference between capacity and a business. Component suppliers arriving, since substrates, leadframes, bonding wire and moulding compound are imported today and a domestic supplier base is the real localisation test. Any published arrangement linking a domestic fab's output to a domestic packaging house. And the first approved project that targets advanced packaging at volume rather than as a pilot. Each is dated and checkable, and each will be recorded here when it happens rather than when it is announced.