Guide

The memory question: India packages memory chips, and fabricates none of them

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

Micron's Sanand plant ships memory modules made in India from wafers made somewhere else, and that sentence is the whole answer.

The answer, stated precisely

India assembles, tests and packages memory chips. India does not fabricate them. Those two sentences are not a technicality, they describe two different industries separated by roughly an order of magnitude in capital and by an entire body of process technology. The plant that makes the distinction concrete is Micron's facility at Sanand in Gujarat, which takes finished memory wafers produced in Micron's fabs outside India and converts them into packaged devices and modules.

Everything that follows explains what that plant does, what a memory fabrication plant would have to be, why the gap between them is not a matter of ambition, and what the public record actually contains on the subject of a future Indian memory fab. Where the record is silent, this page says it is silent rather than filling the space.

It is worth being blunt about the label that causes most of the trouble. A memory module marked as made in India is an accurate label under ordinary rules of origin, because the packaging and module work that confers it happened here. It is not a claim that the silicon inside was grown, patterned and etched here, and the two claims are separated by the most expensive factory in the industry. Reading the label as the second claim is how a genuine industrial achievement gets restated into something the country has not done, which then makes the real achievement harder to defend when someone checks.

What Micron's Sanand plant is

The investment was announced in June 2023 during the Prime Minister's state visit to the United States and cleared under the modified assembly, testing, marking and packaging scheme. The structure is public, per Micron's own announcement and the approval reported that month: a total of about 2.75 billion dollars, of which 825 million dollars comes from Micron, with central fiscal support at 50 percent of total project cost and Gujarat contributing incentives equivalent to 20 percent, for a total outlay reported above Rs 22,500 crore DURABLE. The first phase includes about 500,000 square feet of planned cleanroom space, and Micron has described it as among the largest single-floor assembly and test cleanrooms anywhere.

The plant was inaugurated on 28 February 2026, per Micron's newsroom and the Prime Minister's Office release of that date DURABLE, and Micron marked the opening by presenting the first made-in-India memory modules to Dell for laptops assembled in India. Micron's own framing of the ramp at opening was tens of millions of chips assembled and tested during 2026, scaling to hundreds of millions during 2027 TARGET. The product scope is DRAM and NAND, which covers the memory that goes into data centre servers, artificial intelligence systems, personal computers and phones. Our company file holds the corporate record; this page is about the category question the plant keeps triggering.

What assembly and test does to a memory die, and what it does not

A memory wafer arrives at Sanand already finished. Every transistor, every capacitor, every metal layer and every bit cell was formed in a wafer fab elsewhere, and the electrical fate of each die was largely decided there. What the back end does is real engineering, and it is not fabrication.

• Wafers are thinned and singulated, which means grinding the wafer down and cutting it into individual dies without chipping or cracking them.
• Dies are attached and, for many memory products, stacked, since capacity per package is achieved by putting multiple dies in one body and connecting them.
• Interconnection is formed, classically by wire bonding, and the package is encapsulated to protect the silicon mechanically and environmentally.
• Packaged parts are tested, often at temperature and often for extended periods, because memory failures are frequently pattern-dependent and time-dependent rather than instantly visible.
• Good parts are marked, and in module products they are mounted with a controller or passive components onto a printed circuit substrate, tested again, and shipped.

The value added here is genuine, the yield discipline is genuine, and the test engineering in particular is a serious capability. The packaging and test explainer covers the mechanics. What none of it does is create a bit cell. If the wafers stop arriving, a back-end plant has nothing to process, which is the structural reason no country treats packaging capacity as memory self-sufficiency.

What a memory fab would actually require

Memory fabrication is the most demanding volume manufacturing in the industry, for reasons that are physical before they are financial. A dynamic random access memory cell is one transistor and one capacitor, and the capacitor must hold enough charge to be read reliably while occupying a footprint that shrinks with every generation. That drives extreme aspect ratios, etches that must run straight and clean through very deep structures, and refresh timing that punishes any leakage. NAND flash took the opposite route and went vertical, stacking memory layers in the third dimension, which turns the process into a sequence of alternating depositions followed by high aspect ratio etches through the entire stack, with alignment tolerances that make each additional layer harder than the last.

Around that physics sit four commercial facts. Memory is a commodity, so the product competes almost entirely on cost per bit and the price is set by a global cycle that has repeatedly turned profits into losses within a single year. The industry is consolidated into a very small number of suppliers in each of DRAM and NAND, all of them operating at global scale with decades of accumulated yield learning. The intellectual property position is dense, so a new entrant negotiates rather than invents its way into a process. And the capital cycle differs in kind from a mature-node logic plant, because a memory line stays competitive only by being re-tooled onto each successive generation, so the spending does not stop when the building opens.

That is why a country entering semiconductors rarely starts with memory, and why India's approved portfolio does not. The mature node guide sets out the alternative logic India did choose, which is a specialty and mature CMOS lane with durable industrial demand rather than a commodity race against three incumbents.

Why memory test takes so long, and what that buys a packaging plant

Test is where a memory back end earns its keep, and it explains why an assembly and test plant is a more serious facility than the word packaging suggests. Memory failures are frequently pattern-dependent: a cell holds its charge correctly in isolation and fails when its neighbours are written in a particular order, or fails only at the high end of the temperature range, or fails after hours rather than seconds. Catching those requires writing and reading long, deliberately hostile patterns across the full address space, often at elevated temperature and voltage, which is why memory test time is measured in a way that logic test time usually is not.

Two consequences follow for the plant at Sanand. The first is capital: testers and the handlers that feed them are a large share of a memory back end's equipment bill, and test time directly sets how many units a given tester fleet can ship, which makes test engineering a cost centre and a throughput lever at once. The second is capability: a workforce that can debug pattern-sensitive failures, manage burn-in ovens and repair devices using on-chip redundancy is doing engineering that transfers to any semiconductor plant, including a front-end one. That is a real skills dividend from a plant that does not fabricate anything.

PSMC's memory heritage, and why it does not imply memory at Dholera

Powerchip's history is often cited as evidence that memory is coming to Dholera through the technology partner, so it is worth stating accurately. Powerchip was founded in Taiwan in 1994 and made standard DRAM for its first two decades. The group's published corporate history records its withdrawal from the standard DRAM market around 2012, a repositioning as a professional foundry from 2013, and a restructuring completed in May 2019 that transferred its 12-inch fabs and related business into Powerchip Semiconductor Manufacturing Corporation, the entity that partners Tata at Dholera. The company continues to offer DRAM process technology as a foundry service, which it describes on its own site as a distinguishing capability DURABLE. Our partner file covers the corporate record.

Two further data points sit on that thread and are worth logging without being overread. Powerchip's newsroom published a letter of intent with Micron dated 17 January 2026 concerning specialty DRAM process technology at its Hsinchu P3 fab, and The Register reported on 20 January 2026 that the arrangement involved Micron acquiring a Powerchip fab for about 1.8 billion dollars to expand DRAM output REPORTED. This record has not verified the transaction's completion or its final terms.

None of that changes what is being built in Gujarat. The Dholera approval record specifies a mature and specialty logic profile, with products named as power management chips, display drivers, microcontrollers and logic in a 28 to 110nm band, and no public document commits any memory process to the plant. A partner having a capability in its portfolio is not the same as that capability being transferred, licensed, tooled and qualified at a specific site, and the difference between those two statements is several years and a great deal of capital.

The sourced record of memory-fab talk in India

Checked against the ministry of electronics and information technology's July 2026 portfolio statement, the mission's approved manufacturing base stands at twelve units with cumulative investment stated above Rs 1.64 lakh crore, composed of one silicon fab, one silicon carbide fab, one integrated gallium nitride Micro LED display fab and nine packaging units DURABLE. There is no memory fab in that list. The second phase of the mission, announced in the Union Budget for 2026-27, points the next tranche of policy money at semiconductor equipment and materials manufacturing and at full-stack domestic intellectual property DURABLE, which is a supply-chain agenda rather than a memory agenda.

Nor is there a memory fab proposal on the public record with the attributes that would make it assessable: a named partner with memory process technology, a site, a published capital figure, and a scheme under which it would be funded. Claims that circulate to the contrary usually trace to one of two confusions. The first is treating Sanand as a fab, which it is not. The second is relocating Micron to Dholera, which our answer page exists to correct, and which matters because the relocation error simultaneously inflates what Dholera has secured and misdescribes what Micron built.

What packaging memory is worth anyway

It would be easy to read all of this as a downgrade, and that would be the wrong conclusion. Assembly and test at scale builds a workforce that understands cleanroom discipline, statistical process control, automated handling and high-volume test economics, and those skills transfer upward. It builds customer relationships with global buyers who now have an Indian supply node in their qualification systems, which is not a small thing in an industry where qualification takes years. It creates a demand pull for substrates, chemicals, lead frames, moulding compounds and test consumables, and suppliers follow demand more reliably than they follow subsidy. And it produces an export-capable output from a plant that exists rather than a plan that does not.

The honest limit is that the wafer, not the package, holds most of a memory device's value, so packaging leadership does not confer memory independence. Both statements are true simultaneously, and a record that only prints one of them is selling something.

What would have to change the answer

• A notified scheme or scheme amendment that explicitly covers memory fabrication, since the current instruments were written around logic fabs, compound fabs, displays and packaging.
• A named technology partner, because no Indian entity holds a DRAM or NAND process and no serious proposal appears without one.
• A site with firm power and water at fab scale, published rather than implied, plus the chemical logistics a memory line consumes.
• An approved project with a published capital figure and a phasing schedule, which is the point at which this record would tier it and start scoring it.
• Micron's second phase at Sanand, which the company described as a two-phase project, and whether the scope of that phase remains assembly and test.

Until those appear, the position stated at the top of this page holds without qualification. As of 25 August 2026, memory chips are packaged and tested in India and fabricated elsewhere, and any coverage that blurs the two is describing a country that does not exist yet.