Guide

The chips acts compared: sizes, instruments and delivery records

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

Three governments answered the same question in three different currencies and three different legal forms, which is why their headline numbers cannot simply be lined up next to each other.

What a chips act is actually buying

Every national semiconductor programme of the last four years is an attempt to buy the same three things: physical capacity inside the country's own borders, a supply chain that does not run entirely through two or three foreign addresses, and a workforce that can operate both. The programmes differ in how much money they put behind that purchase, in the legal instrument they use to move it, and in how much of the promised money has actually reached a construction site. This page sets the three most-quoted regimes beside each other on those three axes and refuses to score them on anything else.

One caution belongs at the top, because it invalidates most of the comparisons circulating online. The three headline numbers are not the same kind of number. The American figure is an appropriation by Congress. The European figure is an estimate of investment mobilised across the Commission, member states and private capital. The Indian figure is a central incentive framework, meaning the ceiling of what the government will contribute towards projects that companies pay the larger share of. Treating them as three comparable pots is the single commonest error in coverage of this subject, and this record does not make it.

The United States: appropriation plus tax credit

The CHIPS and Science Act was signed in 2022 and appropriated $52.7 billion for semiconductor research, manufacturing and workforce development. About $39 billion of that sits in the CHIPS for America Fund as manufacturing incentives, with roughly $11 billion directed at research and development programmes. Alongside the appropriation, and separate from it, the Act created an investment credit of 25 percent as enacted, codified at section 48D of the US tax code, which applies to qualifying semiconductor manufacturing equipment expenditure rather than being drawn from the $39 billion.

The delivery record is where the American programme becomes instructive. By 31 January 2025 the CHIPS Program Office at the National Institute of Standards and Technology had awarded 19 companies a total of up to $30.7 billion in funding across 40 commercial fab projects, per the Congressional Research Service in its report on CHIPS-funded fabrication facilities, updated in July 2026 DURABLE. Manufacturing Dive's award tracker, read by this desk on 25 August 2026, records more than $33 billion committed across TSMC, Intel, Samsung, Micron, GlobalFoundries and Bosch. The money is disbursed as reimbursement against completed project milestones rather than as a lump sum on signing, which is why committed and disbursed diverge sharply and why the programme's cash outflow trails its announcements by years.

The programme has also been restructured mid-flight. Manufacturing Dive's tracker records that the Commerce Department removed Natcast as operator of the National Semiconductor Technology Center and voided $7.4 billion of its funding in August 2025 REPORTED. In the same month, part of Intel's award was reported as converted into a US government equity stake of about 9.9 percent in the company, a mechanism the Information Technology and Innovation Foundation argued against in a commentary of 21 August 2025 REPORTED. Whatever one makes of it, the episode is a reminder that a chips act is a political instrument and remains editable by later administrations.

The European Union: a small central budget behind a large headline

The European Chips Act set a target of 20 percent of global semiconductor production value by 2030 and announced at least 43 billion euros of policy-driven investment towards it through the decade, with a similar volume expected from private sources. The structure behind that number is the part most often missed: the European Commission is responsible for only 4.5 billion euros of the 43 billion, with the remainder resting on member state aid and private commitments, as recorded by the European Court of Auditors.

The auditors' verdict is the most useful document in the European file. In its 2025 special report on the Chips Act, the Court of Auditors concluded that the European Union is very unlikely to meet the 20 percent target, noting that reaching it would require roughly quadrupling production capacity by 2030 REPORTED. The Commission's own forecast, published in July 2024, projects the European share of the global value chain rising from 9.8 percent in 2022 to about 11.7 percent by 2030, which is a long way short of the political headline. Euronews reported on 12 May 2025 that member states had asked the Commission to revisit the targets. A programme whose own auditors and own forecasters both say the target will be missed is not a failed programme, but it is a programme whose headline number should never be quoted without its delivery record attached.

India: one capex instrument, applied narrowly

India's programme is younger, smaller and structurally simpler. The Union Cabinet approved the Semicon India Programme in December 2021 with an incentive framework of Rs 76,000 crore, offering fiscal support of up to 50 percent for silicon fabs, compound semiconductor facilities, assembly and testing units and chip design, per the Press Information Bureau backgrounder on India Semiconductor Mission 2.0 dated 7 February 2026 DURABLE. That single up-to-50-percent capital instrument does most of the work, which is a genuine design difference from both the American and European approaches. That description holds for the first phase; the second phase, approved in July 2026 and set out immediately below, is explicitly broader in its stated scope.

The delivery record, stated in the government's own documents: as of December 2025, ten projects with a total investment of Rs 1.60 lakh crore had been approved across six states, per the same 7 February 2026 backgrounder. By June 2026 that had become 12 projects worth around Rs 1.64 lakh crore, per the PIB backgrounder on India's emerging technology ecosystem dated 22 June 2026 DURABLE. Note carefully what that figure is: total project investment, company money and government support combined, across the whole country. It is not government spending, and it is not Dholera's number, though it is regularly misquoted as both. Our capital ledger keeps announced, committed and delivered capital in separate columns for exactly this reason.

The second phase now has a Cabinet decision and a figure behind it, and it is a large one. On 15 July 2026 the Union Cabinet approved Semicon 2.0 for the development of India's semiconductor design and manufacturing ecosystem with a total budget outlay of Rs 1,27,500 crore, per Press Information Bureau release 2284784 of that date, with the same decision published on the Prime Minister's Office website DURABLE. The release presents the programme as sustained long-term support building on the momentum of Semicon 1.0, and describes an ecosystem to be built on six pillars, the first of them design. Alongside it stands a much smaller and quite different number that this record has carried since February: Union Budget 2026-27 provided Rs 1,000 crore for India Semiconductor Mission 2.0 for that financial year, aimed at semiconductor equipment and materials, full-stack Indian intellectual property and supply chain resilience, per the 7 February 2026 backgrounder DURABLE. A multi-year budget outlay approved by Cabinet and a single year's budget provision are two different instruments, and the distance between them is the ordinary distance between a framework and a cash line rather than a contradiction between two sources.

Read the Rs 1,27,500 crore for exactly what it is. It is an approved outlay, meaning the authority to commit money over the life of a programme, and it is neither money spent nor money any company has yet received. What a reader would need next, meaning the scheme-wise division of that outlay, the support rates attached to each pillar and the timetable on which applications open, this desk has not seen published, so the headline is printed here and nothing is invented beneath it. The same release restates the position on the ground: twelve manufacturing units approved with cumulative investment of over Rs 1.64 lakh crore, comprising one silicon fab, one silicon carbide fab, an integrated gallium nitride micro LED display fab and nine packaging units DURABLE. The full programme anatomy sits in our India Semiconductor Mission guide, and the money question alone is answered at what is the ISM budget.

The three regimes on one page

What the Indian model does differently

Three design choices separate the Indian instrument from the other two, and all three are visible in the documents rather than inferred.

• Capital share, not tax credit. The American programme pairs cash awards with a credit that a company can only use against tax it owes, which favours firms already profitable in the United States. India's instrument pays a share of eligible capital expenditure, which is more useful to a first-of-kind plant with no domestic revenue yet, and more expensive to the exchequer in the same breath.
• Explicit state stacking. Gujarat's semiconductor policy adds 40 percent of the capital assistance approved by the central government on top of the central share, alongside land, power and water instruments, per the Gujarat State Electronics Mission. The mechanics and the arithmetic are worked through in how fab incentives work in India. Neither the American nor the European regime formalises a state-plus-centre stack in quite this way, though both see subnational competition.
• A narrow project count. Twelve approved projects is a portfolio a single desk can track individually, and the government publishes each one's investment figure and capacity. That transparency is a real asset for anyone scoring delivery, and it is the reason this record can keep a per-project ledger at all.

What the headline numbers cannot settle

Programme size does not predict programme outcome, and the three delivery records above already show why. The largest appropriation has committed more than $33 billion of its roughly $39 billion manufacturing pot after four years, with cash disbursement trailing that commitment by a wide margin, and has been restructured by a change of administration. The most ambitious market-share target has been declared unreachable by the auditors of the body that set it. The Indian programme, still the smallest of the three on headline size even after the Rs 1,27,500 crore second phase was approved on 15 July 2026, has twelve approved manufacturing units, most of them packaging rather than wafer fabrication, and its flagship fab has not yet produced a commercial chip. An approved outlay is a decision to be able to spend rather than a payment, which is why the second phase belongs in the promises column of the table above and not yet in the delivery column.

There is also a currency and coverage problem that no honest comparison can dissolve. Converting the Indian figures into dollars at any given day's rate, whether the Rs 76,000 crore of the first phase or the Rs 1,27,500 crore approved for the second, produces numbers that look small beside $52.7 billion, but the Indian frameworks buy construction and labour in a different cost base, and they exclude the research funding that makes up roughly a fifth of the American total. Comparing the cost of a single fab, rather than the size of a whole programme, is a cleaner exercise, and this record does it separately.

Finally, none of these programmes buys the thing that actually decides whether a fab succeeds, which is qualified output that customers keep ordering. Subsidy pays for the building and some of the tools. Yield, cycle time and customer qualification are earned afterwards, and no legislature has yet found an instrument that appropriates them.

Portfolio composition, which decides more than size

The two portfolios are built out of different things, and that difference predicts more about outcomes than any currency conversion. The American awards named in Manufacturing Dive's tracker run to TSMC, Intel, Samsung, Micron, GlobalFoundries and Bosch, which is a mix of leading-edge logic, advanced memory, mature-node foundry work and automotive power devices. India's approved portfolio is listed project by project in the 7 February 2026 backgrounder and summarised in the Semicon 2.0 release of 15 July 2026 as twelve manufacturing units: one silicon fab, one silicon carbide fab, an integrated gallium nitride micro LED display fab and nine packaging units, expected to serve consumer appliances, industrial electronics, automobiles, power electronics, telecommunications and aerospace.

That composition is a deliberate sequencing choice rather than an accident, and it changes what delivery looks like. Back-end plants are cheaper, faster to build and easier to staff than wafer fabs, so a portfolio weighted towards them produces visible output sooner and carries less technology risk. It also means India's programme cannot be scored against the American one on first-silicon dates alone, because the two are buying different rungs of the same ladder. The capital ladder between a wafer fab and an assembly plant, which is what that sequencing rests on, is worked through separately on this site.

Workforce funding is the third instrument that rarely appears in headline comparisons. The American act carries workforce development inside its appropriation. India runs its talent programmes as separate, much smaller lines: Chips to Start-up was launched in 2022 with an outlay of Rs 250 crore over five years, per the Press Information Bureau backgrounder of 18 January 2026 DURABLE, and is audited at the C2S programme. Set against a first-phase manufacturing framework of Rs 76,000 crore, the design-talent line is roughly a three-hundredth of the size, and set against the Rs 1,27,500 crore approved for Semicon 2.0 it is roughly a five-hundredth. That ratio is worth keeping in view whenever a programme is described as investing in talent, and it may not hold: design is named as the first of the second phase's six pillars, so the money behind design could grow substantially. What the second phase allocates to training specifically is not stated in the approval release, and this record will read the scheme guidelines when they appear rather than guess at a split now.

One boundary on this page: Japan, South Korea, China and Taiwan all run substantial support programmes of their own, and their figures are frequently quoted in comparison pieces. This desk has not verified those numbers to the standard it applies to the three above, so it prints none of them here rather than passing along a round figure with no document behind it.

What this record will score

Three markers, tracked against these programmes rather than argued about. First, disbursement against commitment: for India, whether payments under the Semicon India Programme move in step with construction, and whether the Rs 1,27,500 crore approved on 15 July 2026 turns into notified schemes, sanctioned projects and released money rather than staying an authorisation on paper, which is the subject of the incentives guide. Second, portfolio composition: whether the Indian portfolio stays weighted towards assembly and test or adds further wafer fabrication capacity, a question our global chips race guide puts in world context. Third, target revision: whether any of the three programmes formally restates a headline target, as European member states have already asked their Commission to consider.

Programmes are judged on what they deliver, on dates, against what they promised. That is the only comparison this desk considers worth publishing, and it is the one that takes the longest to complete.