Guide

US and India semiconductor cooperation: iCET, TRUST and what actually moved

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

Two named frameworks, one large plant, several American entities inside India's approved list, and no public tool order for the Dholera fab.

The framework, with dates

Two named frameworks carry the American side of India's semiconductor story, and both have documented launch dates that are worth separating from the commentary around them.

The Initiative on Critical and Emerging Technology, universally shortened to iCET, was announced in 2022 and launched through its first dialogue in January 2023, with a White House fact sheet dated 31 January 2023 setting out the focus areas. Semiconductors sat alongside artificial intelligence, quantum and wireless telecommunications in that scope DURABLE.

In February 2025 it was succeeded by a framework called Transforming the Relationship Utilizing Strategic Technology, abbreviated TRUST, announced on 13 February 2025 during a visit to Washington. The Office of the Principal Scientific Adviser to the Government of India carries the successor framework on the same page as the original initiative, which is the clearest official confirmation that TRUST is the continuation of iCET rather than a parallel track DURABLE. Its stated scope keeps semiconductors, artificial intelligence and quantum, and adds critical minerals, biotechnology, energy and space.

Those are the facts of the machinery. What follows is an attempt to answer the harder question, which is what the machinery has actually moved.

What a bilateral technology framework can and cannot buy

A framework of this kind is a coordination mechanism between governments. It convenes working groups, it produces joint statements, and it gives officials on both sides a standing reason to resolve friction. Those are real functions and they are worth having. None of them is capital, and none of them is technology.

The distinction is worth holding because of how these frameworks get reported. A joint statement naming semiconductors is not a semiconductor project. A working group on supply chains is not a supply chain. When a plant does get built, it is built because a company made a capital allocation decision under an incentive scheme with a published rulebook, and in India that scheme is the India Semiconductor Mission, whose fabs, compound semiconductor and assembly schemes each offer up to 50 percent fiscal support and whose design linked incentive carries its own outlay of Rs 1,000 crore DURABLE, per the Press Information Bureau backgrounder of 7 February 2026. The policy stack page explains how the central and state layers combine at Dholera.

So the honest test for any framework is downstream of it. Which projects exist, who owns them, and what did the framework contribute that the incentive scheme did not. This page runs that test rather than summarising communiques.

Micron at Sanand: the marquee outcome, filed correctly

The largest American entry in India's semiconductor record is Micron Technology, and the approval predates the TRUST framework and sits alongside the earliest phase of iCET. The Press Information Bureau backgrounder of 7 February 2026 records Micron Technology Inc. establishing a semiconductor manufacturing facility in Gujarat with an investment of Rs 22,516 crore, enabling assembly and test manufacturing for both DRAM and NAND products, with production capacity of around 14 million units per week DURABLE. The project was approved in June 2023.

Two corrections attach to this entry every time it is cited. The plant is at Sanand, near Ahmedabad, not at Dholera, and the two sites are roughly 100 km apart; the answer page exists to kill that confusion, which contaminates a large share of published investment lists. And the plant is a back-end assembly, test and packaging operation rather than a wafer fab, which means India still has no memory fabrication capacity of any kind. Assembling and testing memory is a genuine industrial capability and it is not the same capability as making the die.

The instrument chain behind an entry like this is worth naming once, because it is the same chain every foreign investor in this programme walks, and it is what actually determines whether an announcement becomes a plant. A proposal goes to the India Semiconductor Mission under one of the published schemes. The Union Cabinet clears it, which fixes the eligible cost and the support percentage. A fiscal support agreement is then signed between the government and the project company, which converts an approval into a contractual commitment with disbursement conditions attached. State-level incentives stack on top under the relevant state policy. Only after all four does capital start moving on the terms everyone has been quoting since the first press release.

That chain is why this record separates approvals from agreements from disbursement, and why it treats each as a different tier. An approval is a decision. An agreement is an obligation. A disbursement is money that has actually left the treasury. Coverage routinely collapses the three into the word investment, and a reader who cannot tell which one a headline is describing has no way to judge how far along anything is.

Read at the right scale, Micron is the clearest thing the American lane has produced: a large, real, operating investment by a major US firm, secured under an Indian incentive scheme, in the back end. The company file carries the record, and it belongs on the back-end side of Gujarat's two-node geography rather than beside the fab.

The American names in and around the approved list

Micron is not the only United States entity in India's approved portfolio, and the others are easy to miss because coverage tends to nationalise projects by their most famous name. The Press Information Bureau's own project list is more precise than the coverage of it.

• The CG Power unit in Gujarat, at Rs 7,584 crore, is recorded as a joint venture partnership with Renesas Electronics America Inc., USA, and STARS Microelectronic, Thailand. The technology partner of record is an American-incorporated arm of a Japanese group DURABLE.
• The India Semiconductor Mission's own talent programme runs a large-scale nanofabrication and process engineering training partnership with Lam Research, an American equipment maker, with the stated aim of generating 60,000 trained professionals over ten years TARGET.

One further entry deserves a caution rather than a claim. The same list records 3D Glass Solutions Inc. establishing a facility in Odisha with an investment of Rs 1,943 crore, with proposed installed capacity for glass panel substrate production, assembly and heterogeneous integration of around 5,800 panels per month, 4.20 million units per month and 1,100 units per month respectively DURABLE. Glass panel substrates are an advanced-packaging materials category and the entry is a real one, but the release does not state that company's country of incorporation and this record will not infer it from a corporate suffix.

Neither of the confirmed American entries is attributable to a bilateral framework, and this record does not claim otherwise. What the list does show is that the American corporate presence in India's semiconductor build-out is broader than the single Micron headline, and that it sits in packaging, materials and training rather than in wafer fabrication.

Toolmakers: training programmes are public, purchase orders are not

The equipment layer is where the American corporate presence in this industry is largest and where the Indian record is thinnest. Toolmaking is concentrated: in most process categories the qualified supplier list runs to a handful of firms, and several of the largest of those firms are American. This record does not print category-by-category share figures, because it has not verified any.

For the Dholera fab specifically, the public record contains no purchase order from any American toolmaker, and this desk states that as a finding rather than working around it. The one named lithography engagement is with a European supplier: the memorandum announced on 16 May 2026 by both the ASML and Tata Electronics newsrooms, naming the 28, 40, 55, 90 and 110nm nodes REPORTED. The ASML file carries what that document does and does not commit.

The absence of published American tool orders is not evidence of anything except that companies rarely announce purchase orders. Tool orders leak through other channels: import filings, contractor mobilisation, and the arrival of supplier field service teams on site. This record watches those, because equipment behaviour is the least spinnable evidence a fab project generates.

Export controls at the level this project actually touches

Any page on American semiconductor cooperation eventually meets export controls, and the useful treatment here is mechanical rather than strategic. The general architecture of controls in this industry is that they attach to categories of equipment, software and technology defined by what the item can do rather than to finished products, and the thresholds that attract the most attention sit at the leading edge. This record does not summarise the text of any specific rule, in any jurisdiction, because those rules change and misstating one is worse than omitting it.

The Dholera fab's stated range is 28 to 110nm, and every node in that range is deep ultraviolet territory rather than extreme ultraviolet, as the lithography page explains. Mature-node process equipment in that class is ordinary commercial trade and is sold worldwide. Nothing in the public record indicates any export-control obstacle to the toolset this project requires, and this desk will not speculate about future policy in any jurisdiction. The broader logic of controls, and the arguments made about them, belong on the geopolitics primer rather than here.

The one durable observation worth making is structural. A programme aimed at mature nodes sits well away from the capability thresholds that attract control attention, which means the regulatory environment is not the binding constraint on this build. The binding constraints are civil works, tool installation, process qualification and yield, in that order.

The design layer, where the relationship is oldest and least discussed

The part of the American relationship with Indian semiconductors that predates every framework on this page is design. Large chip companies have run engineering centres in India for decades, and the electronic design automation software that commercial chip design depends on comes from a very small number of vendors, most of them American-headquartered. Neither of those facts arrived through an intergovernmental initiative, and neither is usually counted when the relationship is described.

What the Indian programme has added on top is a funding and access layer with published numbers. The Press Information Bureau backgrounder of 7 February 2026 records that as of January 2026 the design linked incentive scheme supported twenty-four design startups, that those startups had attracted nearly Rs 430 crore in venture funding, that the national design platform had recorded approximately 2.25 crore tool hours of access to high-end design tools, and that the programme's next phase targets enabling at least fifty fabless semiconductor companies.

Two honest observations follow. Tool hours and startup counts measure access and activity, not products shipped, and this record will not treat them as more than that. And the layer they measure is downstream of American software and upstream of any Indian fab, which means design is the one part of the chain where India already participates at scale and the one part where a domestic fab changes the economics rather than creating them. A designer targeting a mature node currently sends the work abroad; a qualified domestic process design kit gives that designer a local option, which is a smaller and more concrete benefit than the phrase self-reliance usually implies. What a domestic fab would and would not change for that layer turns entirely on whether the process design kit it ships is one Indian designers actually want to target.

The honest limits of friend-shoring language

Friend-shoring is a term of art that has done a great deal of work in coverage of India's chip programme, and it deserves a plain reading. As a description of corporate behaviour it means firms adding a second or third manufacturing location for supply security rather than for cost. That behaviour is observable and India has captured some of it.

What the term over-promises is scale and speed. India's approved portfolio as recorded by the Press Information Bureau on 7 February 2026 was ten projects worth Rs 1.60 lakh crore across six states, with one silicon fab among them DURABLE, a figure reported to have risen to twelve units and above Rs 1.64 lakh crore by mid-2026 after further clearances REPORTED. Set against the annual capital spending of the global semiconductor industry, that is an entry rather than a realignment. Claiming more than that is how credibility gets spent.

The measured version is that a set of American, Japanese, Taiwanese and Indian firms have each made a decision to put some capacity in India under a published incentive scheme, that most of that capacity is in packaging and test, and that one wafer fab is under construction. What comes after that, in nodes below 28nm, has no approved project behind it and therefore no date this record would print.

What to watch in the US lane

Four signals, in order of how much they would tell this record. An announced American customer for Dholera output, since customer commitments are the load-bearing signal this project has never produced. A disclosed tool order from a US equipment maker for an Indian fab. Micron publishing verified output or a phase two capital figure for Sanand. And any working-group output under the TRUST framework that names a specific project rather than a category, because a framework that produces named projects is a different instrument from one that produces communiques, and only the first kind belongs on a ledger.