Guide

The Taiwan to India semiconductor bridge: what actually crosses

Published 25 August 2026. Facts verified to 25 August 2026 unless dated otherwise.

Several documented strands connect Taiwan's chip industry to India's build-out, and only one of them is the Dholera fab.

What the Taiwan bridge is actually made of

Coverage of India and Taiwan in semiconductors tends to compress into a single sentence about a strategic friendship. That sentence is not useful to anyone trying to work out whether a fab will run. What is useful is the list of instruments that actually exist, because an instrument has a signature, a date, a scope and a counterparty, and each of those can be checked. This record keeps three.

The first is a process technology licence: Powerchip Semiconductor Manufacturing Corporation of Taiwan supplying the 300mm mature-node flows that the Tata Electronics fab at Dholera will run. The second is Foxconn, which appears twice in the Indian record and only once as a live project. The third is people, moving in the other direction, Indian engineers rotating through Taiwanese fabs for training that cannot be delivered by document. Taiwanese engineering and construction contractors are widely said to be working on Indian semiconductor sites, and this record leaves that strand off the list until a contract is confirmed by a named primary source.

Read together, those three say something more precise than the friendship sentence. What Taiwan is exporting to India is process knowledge, project execution and training capacity in the mature-node range. What it is not exporting, and what nothing in the public record suggests it has been asked to export, is leading-edge capability. That boundary is the single most useful fact about this bridge, and it explains most of what follows.

Strand one: the process licence at Dholera

The Union Cabinet cleared the Tata Electronics fab in Gujarat on 29 February 2024, and the Press Information Bureau backgrounder of 7 February 2026 records the project at Rs 91,526 crore, set up in technology partnership with PSMC, Taiwan, with production capacity of around 50,000 wafer starts per month. The technology transfer agreement between the two companies was completed on 26 September 2024 DURABLE, which is the date this desk treats as the start of the porting exercise rather than the end of it.

Tata's own newsroom describes the arrangement as a build, license and transfer agreement for foundry technology, under which PSMC helps train a seed engineering team from Tata Electronics at a PSMC fab in Taiwan and shares fab automation and design capability alongside the process itself. That description matters because it names the commercial shape. PSMC is a licensor and a service provider on this project. Nothing in the public record describes PSMC taking an equity position in the Dholera fab, and the compensation that has been discussed publicly is consulting, technology transfer and training revenue rather than a share of output.

DigiTimes reported in January 2025 that PSMC expects more than NT$20 billion, roughly US$620 million, from consulting, technology transfer and training across the lifecycle of the engagement REPORTED. Against a project capitalised at Rs 91,526 crore, that is a small fraction of headline cost and a large absolute number for the licensor, which is exactly what a service annuity looks like. The partnership file carries the division of labour in full; this page's interest is narrower, which is what crosses the water and in which direction.

The node range is the other half of the licence, and it is where this record has an open contradiction on file. Tata's official range is 28 to 110nm. Bloomberg reported on 17 July 2026 that the fab will open mostly at 90nm rather than the 28nm that had been promised, and TrendForce carried the same reading on 20 July 2026, while the Tata Sons chairman's FY25 letter had said the fab would start at 28nm. This record presents that contradiction rather than resolving it, and the node investigation holds the evidence. For the Taiwan question specifically, the contradiction changes nothing structural: every node in the disputed range sits inside PSMC's commercial competence and inside deep ultraviolet lithography rather than the extreme ultraviolet class.

Why India got this deal: the Japanese project PSMC walked away from

The Dholera licence did not arrive out of nowhere, and the most instructive context for it is a project that failed in another country. PSMC and Japan's SBI Holdings had announced a wafer fab in Miyagi Prefecture, reported at 40,000 wafers per month starting at 40nm and moving to 28nm, with volume production talked about for 2027. The partnership ended in 2024 and PSMC withdrew from the Japanese project, a sequence reported by TrendForce on 30 September 2024 and by the Taipei Times on 23 October 2024 REPORTED. DigiTimes reporting in October 2024 attributed the withdrawal to PSMC being unwilling to commit to taking responsibility for operating the fab for ten years.

Set that against the Indian structure and the fit becomes legible without any speculation about motives. PSMC's stated model on these engagements is to supply the process, the training and the consulting, and to charge fees and royalties rather than to own and run the plant. A counterparty that wants a licensor to underwrite a decade of operations is asking for something that model does not contain. A counterparty that brings its own balance sheet, its own operating company and its own workforce, and wants the process library and the training, is asking for exactly what the model sells.

The withdrawal also carries a warning worth keeping visible. A licensor that walked away from one national project can walk away from another, and the protection against that is not goodwill but contract structure and the speed at which the licensee builds internal process integration capability. A licence covers the node you bought, not the node after it.

Strand two: Foxconn appears twice, and only once as a live project

Foxconn is the Taiwanese name that shows up most often in Indian semiconductor coverage, and it is the one most often filed wrongly. There are two entries and they belong in different sections of the ledger.

The first is history. The Vedanta and Foxconn semiconductor joint venture collapsed when Foxconn withdrew on 10 July 2023 DURABLE. It should never be presented as live Dholera capital, and the aggregate investment totals that still carry it have simply never been revised downward, which is how cumulative totals drift upward without anyone having to lie. The Vedanta file states what this record does and does not hold on that venture.

The second is live and is not at Dholera. The Press Information Bureau backgrounder of 7 February 2026 lists Vama Sundari Investments (Delhi) Private Limited, the HCL group entity partnering Foxconn, as establishing a semiconductor manufacturing facility in Uttar Pradesh with an investment of Rs 3,706 crore and a production capacity of around 20,000 wafers per month and 36 million chips per month DURABLE. The Union Cabinet cleared it in May 2025, and the foundation stone for the joint venture project was laid on 21 February 2026, per the state broadcaster's news service REPORTED.

Two clarifications keep that entry honest. The unit is a display driver operation, and display drivers are chips, not panels, so it is not a display fab in the panel sense. And the same PIB list sorts India's approved portfolio into one silicon fab, one silicon carbide fab, one integrated gallium nitride micro LED display fab and nine packaging units, which places the Jewar unit on the packaging side of the line rather than the wafer fabrication side. The back-end explainer sets out why that distinction changes the capital, the timeline and the skill base.

Strand three: people, and the part of a fab that cannot be shipped

The least photogenic strand is the one most likely to decide the outcome. Tata Electronics has sent what has been described as a couple of hundred personnel to PSMC in Taiwan for training, reported in batches of around seventy-five people spanning equipment, yield, process technology and quality engineering functions REPORTED.

Those numbers look small next to the employment figures attached to the project, and they are small on purpose. What is being built in Taiwan is not a workforce, it is a seed team. Yield engineering in particular is learned by pattern recognition on real wafer maps under people who have already seen the failure signatures, and there is no document that substitutes for it. A seed team that has run someone else's line comes home able to train the next layer, which is how a fab staffs a floor without importing one.

The arithmetic is worth doing plainly. A fab of this scale needs a technical staff running into the thousands across process, equipment, integration, yield, facilities and quality, and a trained cohort of a few hundred is the first layer of that pyramid rather than the whole of it. Each subsequent layer is trained locally by the layer above, which is why the curve is slow at the start and then steepens. The realistic reading is that this pipeline constrains ramp speed rather than ramp feasibility, and that the constraint is measured in years rather than months. It is also the strand least visible in coverage, because a training cohort produces no photograph of a building.

What a Taiwanese process transfer actually hands over

Technology transfer is a phrase that flatters the transaction. What moves is a library, and most of it is unglamorous. The core deliverable is the process flow, an ordered list of several hundred to well over a thousand individual steps, each specifying a tool type, a chamber configuration, a chemistry, a temperature, a duration and an acceptance window. Around it sit recipe files, run cards, the metrology plan that decides which lots get measured and where, and the statistical process control limits that define when a chamber is out of family and has to be pulled from production.

Alongside the manufacturing flow travels the design enablement package, which is what makes a foundry sellable at all: the process design kit, extracted device models for every transistor flavour and corner, the design rule manual, verification decks, standard cell and input output libraries, memory compilers, and the certification work that makes all of it run inside commercial design tools. A plant that can make wafers but cannot hand a customer a qualified kit is a job shop rather than a foundry.

The third component is qualification, the reliability protocols that turn a working wafer into a part a customer will design in. High temperature operating life, temperature cycling, accelerated stress testing, electromigration and dielectric breakdown characterisation, plus the automotive-grade regimes that power management and microcontroller buyers demand. These consume calendar time and cannot be compressed with capital, which is one reason the commercial production guidance for Dholera sits at mid-2028 rather than earlier TARGET. That guidance came from the electronics and IT minister on 17 July 2026, and it is the only forward date on this project this record treats as scoreable. No supported first-silicon date exists in the public record, and any December 2026 claim circulating for it is unsupported.

The concentration that makes the bridge worth building

The reason a mature-node licence from Taiwan is worth this much administrative effort is the concentration of the industry it comes from. The Press Information Bureau backgrounder of 7 February 2026 states that Taiwan alone produces over 60 percent of the world's semiconductors and nearly 90 percent of the most advanced chips, and that the COVID-19 shortage affected more than 169 industries worldwide DURABLE. Those two facts sit behind every national chip programme now running.

For India the practical consequence is narrow and worth stating without inflation. Buying a mature-node process from Taiwan does not reduce Taiwan's share of anything. It gives India a domestic commercial source for a class of chips it currently imports, and it puts an operating foundry inside the country that domestic designers can eventually target. The mature-node guide makes the commercial case for that class of output.

What is not public, and what to watch

Several things a reader would want are not in the public record, and this desk will not estimate them. The licence terms beyond the headline scope are not public. Whether the agreement covers node migration below the licensed range is not public. The number of PSMC personnel seconded to Dholera at any point in the ramp is not public. No customer for the fab's output has been announced.

Four signals would move this page. First, any disclosure that the licence scope extends beyond the currently named range. Second, tool arrival at Dholera in the lithography class the ASML memorandum of 16 May 2026 named, since that memorandum listed 28, 40, 55, 90 and 110nm and equipment behaviour is the least spinnable evidence there is. Third, a Taiwanese engineering or construction contractor confirmed on an Indian semiconductor site by a named primary source, since that is the strand this page currently cannot evidence. Fourth, the first announced customer, which would tell this record more about the licence than any amount of commentary about the relationship between two countries.